Abstract: Described herein are switches with asymmetrical anti-series varactor pairs to improve switching performance. The disclosed switches can include asymmetrical varactor pairs to reduce distortions. The asymmetry in the varactor pairs can be associated with geometry of each varactor in the pair. The disclosed switches can stack both symmetrical and asymmetrical varactor pairs. The disclosed switches with asymmetrical anti-series varactor pairs can be configured to improve both H2 and H3 simultaneously.

Abstract: A driver circuit includes a first deglitcher circuit that delays a rising edge or a falling edge of an input signal according to a mode control signal and supplies a first output signal. A second deglitcher circuit receives the first output signal and delays either a rising edge or a falling edge of the first output signal by a second delay according to the mode control signal and supplies a second output signal. Logic gates combine the first and second output signals to supply gate control signals for output transistors to drive the driver circuit output. A sum of the first delay and the second delay determines the total deglitch time defining a pulse width of pulses that are suppressed by the driver circuit and the second delay determines a non-overlap time. The non-overlap time overlaps in time with the total deglitch time.

Abstract: Aspects of this disclosure relate to a coupler circuit configured to receive an output of a radio frequency coupler. The coupler circuit can be arranged in a daisy chain with other coupler circuits. The coupler circuit can include a switch configured to turn on based on a signal level of a direct current component of a coupler signal from another coupler circuit and pass a radio frequency component of the coupler signal when on. The coupler circuit can pass the coupler signal while a module that includes the coupler circuit is otherwise inactive.

Abstract: An acoustic wave device that has a better TCF and can improve a resonator Q or impedance ratio is provided. The acoustic wave device includes a substrate 11 containing 70 mass % or greater of silicon dioxide (SiO2), a piezoelectric thin film 12 including LiTaO3 crystal or LiNbO3 crystal and disposed on the substrate 11, and an interdigital transducer electrode 13 disposed in contact with the piezoelectric thin film 12.

Abstract: Envelope tracking systems with modeling for power amplifier supply voltage filtering are provided herein. In certain embodiments, an envelope tracking system includes a supply voltage filter, a power amplifier that receives a power amplifier supply voltage through the supply voltage filter, and an envelope tracker that generates the power amplifier supply voltage. The power amplifier provides amplification to a radio frequency (RF) signal that is generated based on digital signal data, and the envelope tracker generates the power amplifier supply voltage based on an envelope signal corresponding to an envelope of the RF signal. The envelope tracking system further includes digital modeling circuitry that models the supply voltage filter and operates to digitally compensate the digital signal data for effects of the supply voltage filter, such as distortion.

Abstract: A supply-glitch-tolerant voltage regulator includes a regulated voltage node and an output transistor having a source terminal, a gate terminal, and a drain terminal. The source terminal is coupled to the regulated voltage node. The supply-glitch-tolerant voltage regulator includes a first current generator coupled between a first node and a first power supply node. The supply-glitch-tolerant voltage regulator includes a second current generator coupled between the first node and a second power supply node. The supply-glitch-tolerant voltage regulator includes a feedback circuit coupled to the first current generator and the second current generator and is configured to adjust a voltage on the first node based on a reference voltage and a voltage level on the regulated voltage node. The supply-glitch-tolerant voltage regulator includes a diode coupled between the drain terminal and the first power supply node and a resistor coupled between the gate terminal and the first node.

Abstract: Aspects of this disclosure relate to a surface acoustic wave resonator having a multi-layer substrate with heat dissipation. The multi-layer substrate includes a support substrate, a piezoelectric layer, and a thermally conductive layer configured to dissipate heat associated with the surface acoustic wave resonator. The thermally conductive layer is disposed between the support substrate and the piezoelectric layer. Related surface acoustic wave filters, radio frequency modules, and wireless communication devices are also disclosed.

Abstract: Voltage supply system with boost converter and charge pump. A voltage supply system can include a boost converter controllable to receive an input voltage at an input node and generate an output voltage when the output voltage is greater than or equal to the input voltage. The voltage supply system can include a charge pump controllable to receive the input voltage at the input node and generate the output voltage when the output voltage is less than the input voltage. The voltage supply system can further include a controller configured to receive a control signal and control the boost converter or the charge pump to generate the output voltage at an output node based on the control signal.

Abstract: Aspects of this disclosure relate to a surface acoustic wave device. The surface acoustic wave device includes a piezoelectric layer and an interdigital transducer. The interdigital transducer electrode includes a pair of electrodes, each electrode having a bus bar and fingers extending from the bus bar. The interdigital transducer electrode has an interdigital region defined by a portion of the fingers of the electrodes that interdigitate with each other. A dielectric layer is disposed over the interdigital transducer electrode outside the interdigital region and configured to reduce a loss of the surface acoustic wave device.

Abstract: Radio frequency (RF) systems with tunable filters are provided herein. In certain embodiments, an RF system includes a first RF processing circuit configured to process a first frequency band of a first communication standard and a second frequency band of a second communication standard. The first frequency band and the second frequency band are close in frequency and/or partially overlapping in frequency. The first RF processing circuit includes a tunable filter for changing the bandwidth of the first RF processing circuit to enhance the robustness of the first RF processing circuit to blocker or jammer signals of a third frequency band.

Abstract: Aspects of the disclosure provide a front-end module for a wireless device comprising at least one transmit path configured to provide a first sounding reference signal, at least one transmit/receive path coupled to at least one antenna port, a sounding-reference-signal port configured to provide the first sounding reference signal and to receive a second sounding reference signal, an antenna switching module coupled between the at least one transmit path, the at least one transmit/receive path, and the sounding-reference-signal port, the antenna switching module being configured to provide the first sounding reference signal from the transmit path to the at least one transmit/receive path and the sounding-reference-signal port and to provide the second sounding reference signal received at the sounding-reference-signal port to the at least one transmit/receive path.

Abstract: Radio-frequency (RF) switching devices having improved voltage handling capability. In some embodiments, a switching device can include a first terminal and a second terminal, and a plurality of switching elements connected in series to form a stack between the first terminal and the second terminal. The switching elements can have a non-uniform distribution of a parameter that results in the stack having a first voltage handling capacity that is greater than a second voltage handling capacity corresponding to a similar stack having a substantially uniform distribution of the parameter.

Abstract: Signal isolation for module with ball grid array. In some embodiments, a packaged module can include a packaging substrate having an underside, and an arrangement of conductive features implemented on the underside of the packaging substrate to allow the packaged module to be capable of being mounted on a circuit board. The arrangement of conductive features can include a signal feature implemented at a first region and configured for passing of a signal, and one or more shielding features placed at a selected location relative to the signal feature to provide an enhanced isolation between the signal feature and a second region of the underside of the packaging substrate.

Abstract: An integrated circuit includes a demodulator to demodulate a signal simultaneously transmitted over an isolation communication channel and obtain gate information and configuration information. The demodulator includes a gate demodulation path and a configuration demodulation path. The received signal oscillates at a first frequency to represent a first state, oscillates at different frequencies to represent a seconds state, oscillates at a third frequency (or third and fourth frequencies), which are lower than the first frequency, to represent a third state, and the received signal is steady state to represent a fourth state. The gate demodulation path detects the first and second states. The configuration demodulation path includes first and second sub-demodulation paths. An envelope detector in the first sub-demodulation path detects the second state and the second sub-demodulation path detects the third state. The configuration demodulation paths uses an output of the gate demodulation path.

Abstract: Apparatus and methods for power amplifier distortion networks are disclosed. In one aspect, there is provided a power amplifier system including a power amplifier configured to amplify a radio frequency input signal. The power amplifier including an input configured to receive the radio frequency input signal and an output configured to generate an amplified radio frequency signal. The power amplifier system further includes a distortion network electrically coupled to either the input or the output of the power amplifier. The distortion network including a plurality of channelized resistors. The channelized resistors connected in series to either an input or an output of the power amplifier.

Abstract: Disclosed herein are silicon-on-insulator (SOI) switches and associated control circuits having level shifters configured to provide increased voltages (positive and/or negative) to the switches. The disclosed level shifters can be configured to provide increased voltages and can be used with high-linearity switches and/or can improve the linearity of switches. The improved switch performance can improve front end module performance for applications such as carrier aggregation (CA) and multiple input multiple output (MIMO) as well as with protocols such as Long-Term Evolution Advanced (or LTE-A).

Abstract: Apparatus and methods for phase shifters with switched transmission line loads are provided herein. In certain embodiments, a phase shifter includes a first port, a first controllable reflective load, a second port, a second controllable reflective load, and a pair of coupled lines that are electromagnetically coupled to one another. The pair of coupled lines includes a first conductive line between the first port and the first controllable reflective load and a second conductive line between the second controllable reflective load and the second port. At least one of the first controllable reflective load or the second controllable reflective load includes a switched transmission line load.

Abstract: A system delays input clock signals using time-to-digital converters (TDCs) to convert edges or the clock signals to digital values and storing the digital values in a memory. The digital values are retrieved from the memory based on a desired delay. A time counter used by the TDCs to determine the edges is also used determine the delay. The accuracy and range of the delay depends on the time counter and size of the memory.

Abstract: Disclosed herein are signal amplifiers that include a plurality of switchable amplifier architectures so that particular gain modes can use dedicated amplifier architectures to provide desired characteristics for those gain modes, such as low noise figure or high linearity. The disclosed signal amplifier architectures provide tailored impedances using a degeneration block or matrix without using switches in the degeneration switching block. The disclosed signal amplifier architectures provide a plurality of gain modes where different gain modes use different paths through the amplifier architecture. Switches that are used to select the path through the amplifier architecture also provide targeted impedances in a degeneration block or matrix. The switches that select the gain path are provided in the amplifier architecture and are thus not needed or used in the degeneration block, thereby reducing the size of the package for the amplifier architecture.

Abstract: Time of day (ToD) registers provide respective virtual ToDs corresponding to the occurrence of edges of input clock signals being supplied to an integrated circuit. The integrated circuit generates a heartbeat clock signal having a frequency higher than a SYNC signal and time stamps the heartbeat clock signal to generate heartbeat time stamps. The heartbeat time stamps are used along with the time stamps of the input clock signals to determine the time of day corresponding to occurrences of edges of the input clock signals.