Abstract: A method and system for testing memory modules is disclosed. The system includes a memory module and a connector configured to receive the module. The memory module is configured to operate in two modes: In the first operation mode the module uses a frequency between a low frequency and a high frequency. In the second operation mode, the module uses a frequency lower than the lower frequency. A control circuit is coupled to the connector. The control circuit is configured to apply a control signal to the circuit module when the circuit module is received in the connector. When the circuit module is received in the connector, the control signal is applied. This applied control signal causes the module to operate in the second operation mode.

Abstract: A memory supermodule containing two or more memory modules disposed on a common circuit board. Also, a memory supermodule comprising two or more memory modules, each module comprising a circuit board, the circuit boards connected by a flexible circuit. All modules in a supermodule share a single set of contact pads for establishing signal connection with a system in which the supermodule is used.

Abstract: A multilayer printed circuit board (PCB) interface includes a top PCB layer, a middle PCB layer, and a bottom PCB layer. A top surface of the top PCB layer receives at least one top module. The middle PCB layer includes an electrically conductive layer disposed between two dielectric layers. The electrically conductive layer forms a plurality of connectors protruding horizontally from the sides of the multilayer PCB to couple the PCB interface to a main board. A bottom surface of the bottom PCB layer receives at least one bottom module.

Abstract: A circuit for converting signals between a memory interface and a memory array is disclosed. The memory interface is not the same type as the memory array such that the signals between the interface and the array need to be synchronized and translated. The circuit includes an interface converter for shifting the logic levels of the signals between the memory interface and the memory array. Furthermore, the circuit has a translation block for translating and synchronizing the signals. In this respect signals between the memory array and the memory interface are synchronized and translated such that the memory array can be used with a memory interface of a different type.

Abstract: A PCMCIA compatible memory card having a serial communication interface is provided. The serial communication interface includes a controller, a serial transceiver, and a serial communication port. Coupled between the controller and the serial communication port, the transceiver enables the controller to send or receive data through the serial communication port. Nonvolatile memory on the card is accessible by the controller. A cable connects the serial communication port of the memory card to a serial communication port of an external host computer. The controller operates in accordance with commands received from the host computer through the serial communication port of the card for sending data read from memory of the card to the computer, writing data to memory of the card received from the computer, loading a file into memory of the card received from the computer, erasing data from memory of the card, or verifying data in memory on the card.

Abstract: A memory module using non-standard configuration memory devices while allowing access by computer systems is disclosed. In one example, according to the JEDEC standard 2M.times.36 configuration, the memory module is comprised of two banks of 1M deep memory blocks. For this JEDEC standard configuration, the computer system will provide four Row Address Strobe (RAS) signals, four Column Address Strobe (CAS) signals, a Write Enable signal, and ten address signals, A0-A9. The RAS and CAS signals allow memory blocks of the memory banks to be accessed. However, with only ten address signals, only 1M deep memory devices having 1M deep memory locations can be addressed. In order to use 2M deep memory devices having 2M deep memory locations, an eleventh address signal (A10) is needed. A logic circuit is thus provided to derive an additional address signal and to provide the needed refresh cycle for the second 1M memory locations of the 2M deep memory devices.