Abstract: A temperature compensation circuit for a radio frequency power amplifier includes: a temperature control circuit and a negative feedback circuit; the temperature control circuit is configured to generate a first electrical signal corresponding to a temperature, and according to the first electrical signal, adjust a second electrical signal at a first node; the negative feedback circuit is configured to provide, on the basis of the second electrical signal, a negative feedback signal to the radio frequency power amplifier by means of a second node; the second electrical signal is used to change the resistance value of the negative feedback circuit so as to adjust a negative feedback signal that is associated with the resistance value; the negative feedback signal is used to be inputted into the radio frequency power amplifier such that the gain of the radio frequency power amplifier changes.

Abstract: A radio-frequency power amplification circuit includes: a power amplification sub-circuit and an output matching sub-circuit, wherein the power amplification sub-circuit is used for selecting, according to a received control signal corresponding to a radio-frequency mode, a power amplification parameter corresponding to the radio-frequency mode to amplify a received radio-frequency signal, and outputting the amplified radio-frequency signal; the output matching sub-circuit is connected to the power amplification sub-circuit and is used for receiving the amplified radio-frequency signal, and transmitting, according to the control signal, the amplified radio-frequency signal by using an impedance corresponding to the radio-frequency mode.

Abstract: A radio frequency front end module includes an amplifier, a switch and a filter. The switch couples the amplifier with an antenna and connecting the amplifier with the filter, thereby forming a first signal channel in the radio frequency front end module, when a radio frequency signal needs to be transmitted and the transmitted radio frequency signal from a baseband chip needs to be filtered by the radio frequency front end module. The first signal channel can amplify and filter the radio frequency signal transmitted in the first signal channel. The switch can also couples the amplifier with the antenna, thereby forming a second signal channel in the radio frequency front end module, when the transmitted radio frequency signal does not need to be filtered by the radio frequency front end module. The second signal channel can amplify the radio frequency signal transmitted in the second signal channel.

Abstract: A bias circuit includes a first branch circuit, a second branch circuit, a current amplifier and a switch, wherein the first branch circuit is configured to shunt an inputted first current, and input a first branch current of the first current to a power supply ground; the second branch circuit is configured to shunt the inputted first current, and input a second branch current of the first current to the current amplifier; the current amplifier is configured to receive the second branch current of the first current and amplify the second branch current of the first current to serve as a bias current of a power amplifier connected to the bias circuit for outputting; and the switch is configured to switch different resistance values for a resistor in the first branch circuit and/or switch different resistance values for a resistor in the second branch circuit.

Abstract: A power control circuit includes: a voltage-current converter and a programmable current amplifier; the voltage-current converter is configured to detect an inputted output power control signal, and to convert the output power control signal to a control current and output same; and the programmable current amplifier is configured to receive the control current and output the amplified control current as a bias current of the power amplifier connected to the power control circuit.

Abstract: A signal transceiving control structure includes a power amplifier and N control branches. The N control branches are configured to control transmission of first signals or receiving of second signals of different network standards according to different control instructions. First ends of the N control branches are respectively connected to an output end of the power amplifier, second ends of the N control branches are respectively connected to N external output ends, third ends of the N control branches are respectively connected to N external input/output ends, wherein N is a positive integer greater than 1. The power amplifier is configured to perform power amplification on the first signals.

Abstract: A level shifting circuit includes a shift circuit configured to output first and second voltage signals according to level signals, and an input circuit configured to carry out inversion and delay operations on input level signals to obtain first, second, third, and fourth level signals. Rising edge of the first level signal is earlier than falling edge of the second level signal by a first preset time. Falling edge of first level signal is later than rising edge of the second level signal by a second preset time; the third level signal is obtain by delaying the first level signal by a third preset time, and the fourth level signal is obtain by delaying the second level signal by a fourth preset time; the first preset time is longer than the third preset time, and the second preset time is longer than the fourth preset time.

Abstract: A Miller compensation circuit includes: a differential amplifier having an inverse input end configured to receive an input signal; an output transistor having an output end connected to a positive input end of the differential amplifier, a first end connected to a first power supply, a second end connected to an output end of the differential amplifier, and a third end being a voltage output end and connected to the positive input end and a load; a Miller capacitor connected to the output end of the differential amplifier; a follower; and a current sampling circuit configured to sample a first current of the output transistor. The load is also connected to a second power supply.

Abstract: A power control circuit includes a voltage control circuit and a current control circuit. The voltage control circuit is configured to detect an output power control signal that is inputted, convert the output power control signal into a control voltage and output the control voltage to the driver stage of a power amplifier connected to the power control circuit. The current control circuit is configured to detect an output power control signal that is inputted, convert the output power control signal into a control current and output the control current to the amplification stage of the power amplifier.

Abstract: A signal amplifier includes one or more driver stage amplifiers and a power stage amplifier. The one or more driver stage amplifiers are connected in series. The one or more driver stage amplifiers and the power stage amplifier are connected to the same power supply, such that each of the at least one driver stage amplifier forms a loop with the power stage amplifier. The signal amplifier can further include a wave trap unit configured to block an oscillation frequency in the loop. One terminal of the wave trap unit is connected to the loop. The other terminal of the wave trap unit is grounded.

Abstract: A transistor circuit of low shutoff-state current includes: a first transistor, a transistor string, and a switch. The first transistor and the transistor string are connected in series. The switch is configured to shut off the circuit. The first transistor is configured to reduce the shutoff-state current flowing therethrough using the negative feedback effect of the transistor string when the circuit is in a shutoff state; and the transistor string is configured to reduce the shutoff-state current flowing therethrough using a negative gate-source electrode voltage difference thereof and the bulk effect of the transistor.

Abstract: A silicon-on-insulator (SOI) based positive/negative voltage generation circuit includes: an inverter including an NMOS transistor and a PMOS transistor, a first transfer capacitor coupled to the PMOS transistor, a first output capacitor, a second transfer capacitor coupled to the NMOS transistor, a second output capacitor, a first diode disposed between the first transfer capacitor and the first output capacitor, a second diode disposed between the second transfer capacitor and the second output capacitor, one end of the first output capacitor is coupled to the ground, one end of the second output capacitor is coupled to the ground; wherein an output voltage of the inverter is controlled by a single-phase clock to flip periodically, charge the first transfer capacitor through a parasitic diode of the PMOS transistor, and charge the second transfer capacitor through a parasitic diode of the NMOS transistor.

Abstract: A charge pump is designed to be capable of quick start up. When the enable signal of the charge pump is arrived, the pump capacitor and the load capacitor of the charge pump can be charged in a short time, referred to as a pre-charging stage. During the normal working period, the pump capacitor and the output capacitor are controlled by the proper switch that is configured into the connection relationship that the charge pump can normally work in order to make the charge pump work normally. As a result of the pre-charge operation, embodiments disclosed herein can reduce the time of the output capacitor for reaching a steady state value.

Abstract: A silicon-on-insulator (SOI) based positive/negative voltage generation circuit includes: an inverter including an NMOS transistor and a PMOS transistor, a first transfer capacitor coupled to the PMOS transistor, a first output capacitor, a second transfer capacitor coupled to the NMOS transistor, a second output capacitor, a first diode disposed between the first transfer capacitor and the first output capacitor, a second diode disposed between the second transfer capacitor and the second output capacitor, one end of the first output capacitor is coupled to the ground, one end of the second output capacitor is coupled to the ground; wherein an output voltage of the inverter is controlled by a single-phase clock to flip periodically, charge the first transfer capacitor through a parasitic diode of the PMOS transistor, and charge the second transfer capacitor through a parasitic diode of the NMOS transistor.

Abstract: A small-sized rapid transition Schmitt trigger circuit for use with a silicon-on-insulator process includes: a first NMOS transistor, a first PMOS transistor, a second NMOS transistor, a second PMOS transistor, and a PMOS/NMOS body control circuit; wherein, the PMOS/NMOS body control circuit is configured to, through changing threshold voltages of the first NMOS transistor and the first PMOS transistor, enable different flip-flop threshold voltages for input transitions from high electrical levels to low electrical levels and from low electrical levels to high electrical levels.

Abstract: A transistor circuit of low shutoff-state current includes: a first transistor, a transistor string, and a switch. The first transistor and the transistor string are connected in series. The switch is configured to shut off the circuit. The first transistor is configured to reduce the shutoff-state current flowing therethrough using the negative feedback effect of the transistor string when the circuit is in a shutoff state; and the transistor string is configured to reduce the shutoff-state current flowing therethrough using a negative gate-source electrode voltage difference thereof and the bulk effect of the transistor.

Abstract: A charge pump is designed to be capable of quick start up. When the enable signal of the charge pump is arrived, the pump capacitor and the load capacitor of the charge pump can be charged in a short time, referred to as a pre-charging stage. During the normal working period, the pump capacitor and the output capacitor are controlled by the proper switch that is configured into the connection relationship that the charge pump can normally work in order to make the charge pump work normally. As a result of the pre-charge operation, embodiments disclosed herein can reduce the time of the output capacitor for reaching a steady state value.

Abstract: The present invention provides a single chain power amplifier for a multi-mode and/or multi band wireless communication. The power amplifier comprise switchable input, inter-stage and output matching networks as well as active periphery adjustable driver stage power device and power stage power device. Switches and bias are configured for each frequency band and/or wireless communication standard. A driver stage power device, switches, control and bias circuitry, input matching, inter-stage matching and a part of output matching is fabricated on CMOS Silicon On Insulator process (SOI), while a power stage power device maybe fabricated by Gallium Arsenide (GaAs) processing.