Patents Assigned to Sofics BVBA
  • Publication number: 20180166876
    Abstract: An electrostatic discharge (ESD) protection device with a high holding voltage is disclosed including at least an ESD clamp coupled to a holding voltage tuning circuit. The ESD clamp may be coupled to the holding voltage tuning circuit through a connection circuit such as a diode. The ESD clamp may be implemented by a first silicon controlled rectifier (SCR) and the holding voltage tuning circuit may be implemented as a second SCR.
    Type: Application
    Filed: January 24, 2018
    Publication date: June 14, 2018
    Applicant: Sofics BVBA
    Inventor: Sven Van Wijmeersch
  • Publication number: 20180006016
    Abstract: Disclosed is an electrostatic discharge (ESD) protection circuit. The ESD protection circuit may include a silicon controller rectifier (SCR) which may be triggered via at least one of its first trigger gate or second trigger gate. The ESD protection circuit may further include a highly doped region coupled to either the anode or cathode of the SCR, wherein the highly doped region may provide additional carriers to facilitate triggering of the SCR during an ESD event, whereby the SCR may be triggered more quickly.
    Type: Application
    Filed: June 16, 2017
    Publication date: January 4, 2018
    Applicant: Sofics BVBA
    Inventors: Bart Sorgeloos, Benjamin Van Camp, Olivier Marichal
  • Publication number: 20170243864
    Abstract: An electrostatic discharge (ESD) protection device is disclosed including at least an NPN transistor and a PNP transistor coupled between a first node and a second node, wherein the ESD protection device may be configured to sink current from the first node to the second node in response to an ESD event. The transistors may be coupled such that a collector of the NPN may be coupled to the first node. A collector of the PNP may be coupled to the second node. A base of the NPN may be coupled to the emitter of the PNP. An emitter of the NPN may be coupled to a base of the PNP.
    Type: Application
    Filed: May 5, 2017
    Publication date: August 24, 2017
    Applicant: Sofics BVBA
    Inventors: Bart Sorgeloos, Benjamin Van Camp, Sven Van Wijmeersch, Wim Vanhouteghem
  • Patent number: 9653453
    Abstract: An electrostatic discharge (ESD) protection device is disclosed including at least an NPN transistor and a PNP transistor coupled between a first node and a second node, wherein the ESD protection device may be configured to sink current from the first node to the second node in response to an ESD event. The transistors may be coupled such that a collector of the NPN may be coupled to the first node. A collector of the PNP may be coupled to the second node. A base of the NPN may be coupled to the emitter of the PNP. An emitter of the NPN may be coupled to a base of the PNP.
    Type: Grant
    Filed: May 23, 2016
    Date of Patent: May 16, 2017
    Assignee: Sofics BVBA
    Inventors: Bart Sorgeloos, Benjamin Van Camp, Sven Van Wijmeersch, Wim Vanhouteghem
  • Publication number: 20160268250
    Abstract: An electrostatic discharge (ESD) protection device is disclosed including at least an NPN transistor and a PNP transistor coupled between a first node and a second node, wherein the ESD protection device may be configured to sink current from the first node to the second node in response to an ESD event. The transistors may be coupled such that a collector of the NPN may be coupled to the first node. A collector of the PNP may be coupled to the second node. A base of the NPN may be coupled to the emitter of the PNP. An emitter of the NPN may be coupled to a base of the PNP.
    Type: Application
    Filed: May 23, 2016
    Publication date: September 15, 2016
    Applicant: Sofics BVBA
    Inventors: Bart Sorgeloos, Benjamin Van Camp, Sven Van Wijmeersch, Wim Vanhouteghem
  • Patent number: 9349716
    Abstract: An electrostatic discharge (ESD) protection device is disclosed including at least an NPN transistor and a PNP transistor coupled between a first node and a second node, wherein the ESD protection device may be configured to sink current from the first node to the second node in response to an ESD event. The transistors may be coupled such that a collector of the NPN may be coupled to the first node. A collector of the PNP may be coupled to the second node. A base of the NPN may be coupled to the emitter of the PNP. An emitter of the NPN may be coupled to a base of the PNP.
    Type: Grant
    Filed: February 6, 2013
    Date of Patent: May 24, 2016
    Assignee: Sofics BVBA
    Inventors: Bart Sorgeloos, Benjamin Van Camp, Sven Van Wijmeersch, Wim Vanhouteghem
  • Patent number: 9041054
    Abstract: A high holding voltage (HV) electrostatic discharge (ESD) protection circuit comprises a silicon controlled rectifier (SCR) device and compensation regions located within the length between the anode and cathode (LAC) of the SCR device which increase the holding voltage of the SCR device. The compensation regions may introduce negative feedback mechanisms into the SCR device which may influence the loop gain of the SCR and cause it to reach regenerative feedback at a higher holding voltage.
    Type: Grant
    Filed: February 14, 2014
    Date of Patent: May 26, 2015
    Assignee: Sofics BVBA
    Inventors: Sven Van Wijmeersch, Olivier Marichal
  • Patent number: 9042065
    Abstract: An electrostatic discharge (ESD) protection circuit is disclosed including at least a clamping device, a switching device, and a voltage limiter. The ESD protection circuit may include devices of different voltage domains. The switching device may be in series with the clamping device to block at least a portion of a voltage from dropping across the clamping device. The switching device may sustain higher maximum operating voltages than the clamping device.
    Type: Grant
    Filed: December 7, 2012
    Date of Patent: May 26, 2015
    Assignee: Sofics BVBA
    Inventors: Sven Van Wijmeersch, Benjamin Van Camp, Olivier Marichal, Johan Van der Borght
  • Patent number: 8922960
    Abstract: An improved ESD protection circuit having an ESD device and a triggering device to provide a continuously adjustable trigger voltage. This can be accomplished by various techniques such as placing a selected number of triggering elements in series, modifying the gate control circuitry and varying the size of the triggering elements.
    Type: Grant
    Filed: July 8, 2009
    Date of Patent: December 30, 2014
    Assignee: Sofics BVBA
    Inventor: Sven Van Wijmeersch
  • Patent number: 8830641
    Abstract: An electrostatic discharge (ESD) protection device is disclosed. The ESD protection circuit is configured to operate in high voltage domains. The ESD protection device may further include stacked NMOS or PMOS devices. The gates of the MOS devices may be driven by respective inverters. The inverters may be coupled to a voltage divider and may be triggered by respective trigger circuits. Power nodes of the inverters may be connected such that devices in the ESD protection circuit are exposed to voltages that are within their maximum voltage rating.
    Type: Grant
    Filed: March 4, 2013
    Date of Patent: September 9, 2014
    Assignee: Sofics BVBA
    Inventors: Johan Van Der Borght, Sven Van Wijmeersch, Benjamin Van Camp, Bart Sorgeloos
  • Patent number: 8653557
    Abstract: A high holding voltage (HV) electrostatic discharge (ESD) protection circuit comprises a silicon controlled rectifier (SCR) device and compensation regions located within the length between the anode and cathode (LAC) of the SCR device which increase the holding voltage of the SCR device. The compensation regions may introduce negative feedback mechanisms into the SCR device which may influence the loop gain of the SCR and cause it to reach regenerative feedback at a higher holding voltage.
    Type: Grant
    Filed: February 17, 2011
    Date of Patent: February 18, 2014
    Assignee: Sofics BVBA
    Inventors: Sven Van Wijmeersch, Olivier Marichal
  • Patent number: 8537514
    Abstract: The present invention provides an ESD protection device having at least one diode in a well of first conductivity type formed in a substrate of second conductivity type. The circuit further includes a guard-band of the first conductivity surrounding at least a portion of the diode, thus forming an NPN transistor between the diode cathode, the substrate and the guard-band.
    Type: Grant
    Filed: February 8, 2012
    Date of Patent: September 17, 2013
    Assignee: Sofics BVBA
    Inventors: Benjamin Van Camp, Geert Wybo, Stefaan Verleye
  • Publication number: 20130200493
    Abstract: An electrostatic discharge (ESD) protection device is disclosed including at least an NPN transistor and a PNP transistor coupled between a first node and a second node, wherein the ESD protection device may be configured to sink current from the first node to the second node in response to an ESD event. The transistors may be coupled such that a collector of the NPN may be coupled to the first node. A collector of the PNP may be coupled to the second node. A base of the NPN may be coupled to the emitter of the PNP. An emitter of the NPN may be coupled to a base of the PNP.
    Type: Application
    Filed: February 6, 2013
    Publication date: August 8, 2013
    Applicant: Sofics BVBA
    Inventor: Sofics BVBA
  • Publication number: 20130163128
    Abstract: An electrostatic discharge (ESD) protection circuit is disclosed including at least a clamping device, a switching device, and a voltage limiter. The ESD protection circuit may include devices of different voltage domains. The switching device may be in series with the clamping device to block at least a portion of a voltage from dropping across the clamping device. The switching device may sustain higher maximum operating voltages than the clamping device.
    Type: Application
    Filed: December 7, 2012
    Publication date: June 27, 2013
    Applicant: Sofics BVBA
    Inventor: Sofics BVBA
  • Patent number: 8283698
    Abstract: An electrostatic discharge (ESD) protection circuit for protecting an integrated circuit (IC) having a first voltage potential, a first power supply potential and a second power supply potential. The ESD circuit includes a first NPN bipolar transistor having a first N-doped junction, a second N-doped junction and a third P-doped base junction. The first N-doped junction is coupled to the first voltage potential and the second N-doped junction is coupled to the first power supply potential. The ESD circuit also includes a first PNP bipolar transistor having a first P-doped junction, a second P-doped junction and a third N-doped base junction. The first P-doped junction is coupled to the first voltage potential and the second P-doped junction is coupled to the second power supply potential. The third P-doped base junction of the first NPN bipolar transistor is coupled to the third N-doped base junction of the first PNP bipolar transistor.
    Type: Grant
    Filed: April 15, 2010
    Date of Patent: October 9, 2012
    Assignee: Sofics BVBA
    Inventors: Bart Sorgeloos, Benjamin Van Camp
  • Patent number: 8247839
    Abstract: An ESD protection circuit including an SCR having at least one PNP transistor and at least one NPN transistor such that at least one of the PNP transistor and the NPN transistor having an additional second collector. The circuit further including at least one control circuit coupled to the at least one second collector to control holding voltage of the SCR.
    Type: Grant
    Filed: July 9, 2009
    Date of Patent: August 21, 2012
    Assignee: Sofics BVBA
    Inventor: Sven Van Wijmeersch
  • Patent number: 8164869
    Abstract: The present invention provides an ESD protection device having at least one diode in a well of a first conductivity type formed in a substrate of a second conductivity type. The circuit further includes a guard-band of the first conductivity surrounding at least a portion of the diode, thus forming an NPN transistor between the diode cathode, the substrate and the guard-band.
    Type: Grant
    Filed: August 8, 2008
    Date of Patent: April 24, 2012
    Assignee: Sofics BVBA
    Inventors: Benjamin Van Camp, Geert Wybo, Stefaan Verleye
  • Patent number: 8143700
    Abstract: The present invention provides an electrostatic discharge (ESD) protection circuit with a silicon controlled rectifier (SCR) having a plurality of SCR fingers (SCRs) with the advantages to couple the different fingers or SCRs to decrease the multi-triggering problem and to increase the ESD-performance of the circuit. Additionally, a boost circuit can be introduced or additionally multiple SCRs can be coupled inherent through a common base.
    Type: Grant
    Filed: December 29, 2008
    Date of Patent: March 27, 2012
    Assignee: Sofics BVBA
    Inventors: Pieter Vanysacker, Benjamin Van Camp, Olivier Marichal, Wybo Geert, Steven Thijs, Gerd Vermont
  • Patent number: 7986502
    Abstract: An ESD protection circuit including an SCR having at least a PNP transistor and at least a NPN transistor such that said PNP transistor is coupled to an anode and the NPN transistor is coupled to a cathode. The circuit also includes a first resistor coupled between the anode and the base of the pnp transistor and a second resistor coupled between the cathode and the base of the npn transistor. A parasitic distributed bipolar transistor is formed between said first and second transistor to control triggering of the SCR.
    Type: Grant
    Filed: July 9, 2009
    Date of Patent: July 26, 2011
    Assignee: Sofics BVBA
    Inventor: Bart Sorgeloos
  • Patent number: 7973334
    Abstract: The present invention provides an ESD device to reduce the total triggering current without increasing the overshoot voltage. This is achieved by localizing the triggering current, such that the local current density remains high enough to trigger the ESD device. This localized triggering provides a fast and efficient triggering of the ESD device.
    Type: Grant
    Filed: August 15, 2008
    Date of Patent: July 5, 2011
    Assignee: Sofics BVBA
    Inventors: Stefaan Verleye, Geert Wybo, Benjamin Van Camp