Patents Assigned to Solid State Measurements, Inc.
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Patent number: 7007408Abstract: To remove and/or prevent contamination of a probe, at least a portion of the probe is positioned in a chamber having an inlet passage and an outlet passage, with a distal end of the probe extending through the outlet passage and terminating on a side thereof opposite the chamber. A gas is caused to flow through the inlet passage into the chamber and out the outlet passage, thereby modifying an environment surrounding the distal end of the probe. The gas may be heated prior to injection.Type: GrantFiled: April 28, 2004Date of Patent: March 7, 2006Assignee: Solid State Measurements, Inc.Inventors: William H. Howland, Jr., James E. Healy, Jr.
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Patent number: 7005307Abstract: To detect soft breakdown of a dielectric layer of a semiconductor wafer, a DC current is caused to flow between a top surface of the dielectric layer and the semiconducting material of the semiconductor wafer. The DC current is either a constant value DC current, or a DC current that swept and/or stepped from a first value toward a second value in a manner whereupon the electric field and, hence, a DC voltage induced across the dielectric layer increases as the DC current approaches the second value. The response of the semiconductor wafer to the flow of DC current is measured for the presence of an AC voltage component superimposed on the DC voltage. The value of the DC voltage induced across the dielectric layer where the AC voltage component is detected is designated as the soft breakdown voltage of the dielectric layer.Type: GrantFiled: June 28, 2004Date of Patent: February 28, 2006Assignee: Solid State Measurements, Inc.Inventors: William H. Howland, Jr., Robert J. Hillard
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Patent number: 6991948Abstract: A method of characterizing a silicon-on-insulator (SOI) wafer, comprised of an insulating layer sandwiched between a semiconductor top layer and a semiconductor substrate, includes moving a pair of spaced conductors into contact with a surface of the wafer exposed on a side thereof opposite the substrate. First and second biases are applied to the substrate and at least one of the conductors. At least one of the first and second biases are swept from a first value toward a second value and the current flowing through the SOI wafer in response to said sweep is measured. At least one characteristic of the wafer is determined from the measured current as a function of the one swept bias.Type: GrantFiled: November 5, 2003Date of Patent: January 31, 2006Assignee: Solid State Measurements, Inc.Inventor: Robert J. Hillard
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Publication number: 20050287684Abstract: To detect soft breakdown of a dielectric layer of a semiconductor wafer, a DC current is caused to flow between a top surface of the dielectric layer and the semiconducting material of the semiconductor wafer. The DC current is either a constant value DC current, or a DC current that swept and/or stepped from a first value toward a second value in a manner whereupon the electric field and, hence, a DC voltage induced across the dielectric layer increases as the DC current approaches the second value. The response of the semiconductor wafer to the flow of DC current is measured for the presence of an AC voltage component superimposed on the DC voltage. The value of the DC voltage induced across the dielectric layer where the AC voltage component is detected is designated as the soft breakdown voltage of the dielectric layer.Type: ApplicationFiled: June 28, 2004Publication date: December 29, 2005Applicant: Solid State Measurements, Inc.Inventors: William Howland, Robert Hillard
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Publication number: 20050287683Abstract: To determine the generation lifetime of a pn junction of a semiconductor wafer, an elastically deformable, electrically conductive contact is caused to touch a surface of the semiconductor wafer over the pn junction. At least one reverse bias voltage is applied to the pn junction via the contact and a value of current flowing in the contact in response to the application of each reverse bias voltage is measured. The generation lifetime of the pn junction is then determined from a subset of the values of the reverse bias voltage and the corresponding values of measured current.Type: ApplicationFiled: June 23, 2004Publication date: December 29, 2005Applicant: Solid State Measurements, Inc.Inventor: Robert Hillard
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Patent number: 6972582Abstract: An apparatus for measuring at least one electrical property of a semiconductor wafer includes a probe including a shaft having at a distal end thereof a conductive tip for electrically communicating with an object area of the semiconductor wafer. The apparatus further includes a device for applying an electrical stimulus between the conductive tip and the object area, and a device for measuring a response of the semiconductor wafer to the electrical stimulus and for determining from the response the at least one electrical property of the object area of the semiconductor wafer. A probe guard is included that surrounds the shaft of the probe adjacent the distal end of the probe. The probe guard avoids electrical communication between the probe and areas outside of the object area of the semiconductor wafer.Type: GrantFiled: February 10, 2003Date of Patent: December 6, 2005Assignee: Solid State Measurements, Inc.Inventors: William H. Howland, Robert G. Mazur
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Publication number: 20050253618Abstract: In a method of measuring at least one electrical property of a semiconductor wafer, an elastically deformable conductive contact formed from an electrically conductive coating overlaying an electrically conductive base material is provided. The base material has a first work function and the coating has a second work function. A first electrical contact is formed between the conductive contact and a top surface of a semiconductor wafer. A second electrical contact is formed with the semiconductor wafer. An electrical stimulus is applied between the first and second electrical contacts and a response of the semiconductor wafer to the electrical stimulus is measured. At least one electrical property of the semiconductor wafer is determined from the response.Type: ApplicationFiled: May 14, 2004Publication date: November 17, 2005Applicants: Solid State Measurements, Inc., Applied Materials, Inc.Inventors: William Howland, Robert Hillard, Steven Hung
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Publication number: 20050241175Abstract: To remove and/or prevent contamination of a probe, at least a portion of the probe is positioned in a chamber having an inlet passage and an outlet passage, with a distal end of the probe extending through the outlet passage and terminating on a side thereof opposite the chamber. A gas is caused to flow through the inlet passage into the chamber and out the outlet passage, thereby modifying an environment surrounding the distal end of the probe. The gas may be heated prior to injection.Type: ApplicationFiled: April 28, 2004Publication date: November 3, 2005Applicant: Solid State Measurements, Inc.Inventors: William Howland, James Healy
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Publication number: 20050225345Abstract: A sheet resistance test of a wafer or sample can be performed by causing a plurality of spaced contacts, each of which either does not form oxides thereon or which forms conductive oxides thereon, to touch a surface of the wafer without penetrating or damaging the surface. An electrical stimulus is then applied to the wafer via one or more of the contacts and the electrical response of the semiconducting material to the electrical stimulus is detected via one or more of the contacts. At least one electrical property of the wafer can be determined from the measured response and the applied electrical stimulus.Type: ApplicationFiled: April 5, 2005Publication date: October 13, 2005Applicant: Solid State Measurements, Inc.Inventors: Robert Mazur, Robert Hillard, James Healy
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Patent number: 6900652Abstract: A measuring apparatus for measuring a semiconductor wafer, or a film or coating thereon, includes an electrically conductive wafer chuck and a probe having a probe body defining an internal cavity in fluid communication with an electrically conductive and elastic or resilient membrane. The membrane and a topside of the semiconductor wafer are moved into spaced relation when the semiconductor wafer is supported by the wafer chuck. A pressure of fluid supplied to the internal cavity of the probe body is selectively controlled whereupon the membrane expands into contact with the topside of the semiconductor wafer. A suitable test stimulus is applied to the membrane and the semiconductor wafer and the response of the semiconductor wafer to the test stimulus is measured.Type: GrantFiled: June 13, 2003Date of Patent: May 31, 2005Assignee: Solid State Measurements, Inc.Inventor: Robert G. Mazur
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Patent number: 6894519Abstract: An apparatus for measuring an electrical property of a semiconductor wafer includes a probe having an electrically conductive tip formed at least in part of a material that is transparent to light and a probe guard disposed adjacent the electrically conductive tip. The apparatus includes a device for selectively applying a first electrical stimulus between a semiconductor wafer and the electrically conductive tip of each probe when it is positioned in spaced relation to the semiconducting material forming the semiconductor wafer, and a device for selectively applying a second electrical stimulus between the semiconductor wafer and the probe guard of each probe. A device for measuring a response of the semiconductor wafer to the electrical stimuli and for determining from the response at least one electrical property thereof is provided. A light source can be positioned to selectively emit light through the transparent material toward the semiconductor wafer.Type: GrantFiled: April 11, 2002Date of Patent: May 17, 2005Assignee: Solid State Measurements, Inc.Inventor: William H. Howland
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Patent number: 6879176Abstract: A leakage current of a dielectric overlaying a semiconductor wafer can be determining by moving a conductive probe into contact with the dielectric and applying an electrical stimulus, in the form of a fixed amplitude, fixed frequency AC voltage superimposed on a DC voltage which is swept from a starting voltage towards an ending voltage, between the probe tip and the semiconductor wafer. Conductance values associated with the dielectric and the semiconductor wafer can be determined from phase angles between the AC voltage and an AC current resulting from the applied AC voltage during the sweep of the DC voltage. The leakage current of the dielectric can then be determined from the thus determined conductance values.Type: GrantFiled: November 4, 2003Date of Patent: April 12, 2005Assignee: Solid State Measurements, Inc.Inventor: Robert J. Hillard
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Patent number: 6851096Abstract: A wafer testing apparatus comprises a sample chuck having a flat surface for supporting a test wafer positioned thereon, the sample chuck having a base structure manufactured of a conductive metal and having a semiconductor layer secured to the base structure defining the flat surface of the sample chuck, an electrical test probe establishing a correction factor corresponding to a location on the semiconductor layer surface to be used to report an electrical property at a location on a test wafer substantially unaffected by the electrical properties of the semiconductor layer and base structure below that location.Type: GrantFiled: August 8, 2002Date of Patent: February 1, 2005Assignee: Solid State Measurements, Inc.Inventor: William J. Alexander
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Patent number: 6842029Abstract: A multi-probe assembly includes a chuck assembly configured to receive a back or front surface of a semiconductor wafer. A multi-probe holder has a plurality of probes each having an elastically deformable conductive tip movable into contact with a front surface of a dielectric or a front surface of a semiconducting material. A means applies an electrical stimulus to each tip, measures a response to the electrical stimulus, and determines at least one electrical property of the dielectric and/or the semiconducting material. A method for measuring at least one electrical property applies a probe (or plurality of probes) having an elastically deformable conductive tip to a scribe line(s). An electrical stimulus is applied to the probe or one of the probes with the remaining probes grounded. A response to the electrical stimulus is measured and at least one electrical property of the semiconductor wafer is determined from the response.Type: GrantFiled: April 11, 2002Date of Patent: January 11, 2005Assignee: Solid State Measurements, Inc.Inventor: William H. Howland
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Publication number: 20040251923Abstract: A measuring apparatus for measuring a semiconductor wafer, or a film or coating thereon, includes an electrically conductive wafer chuck and a probe having a probe body defining an internal cavity in fluid communication with an electrically conductive and elastic or resilient membrane. The membrane and a topside of the semiconductor wafer are moved into spaced relation when the semiconductor wafer is supported by the wafer chuck. A pressure of fluid supplied to the internal cavity of the probe body is selectively controlled whereupon the membrane expands into contact with the topside of the semiconductor wafer. A suitable test stimulus is applied to the membrane and the semiconductor wafer and the response of the semiconductor wafer to the test stimulus is measured.Type: ApplicationFiled: June 13, 2003Publication date: December 16, 2004Applicant: Solid State Measurements, Inc.Inventor: Robert G. Mazur
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Patent number: 6803780Abstract: A sample chuck for supporting sample semiconductor wafers during testing includes an upper layer formed from a semiconducting material laminated to a lower layer formed from a conducting material.Type: GrantFiled: May 3, 2002Date of Patent: October 12, 2004Assignee: Solid State Measurements, Inc.Inventors: Michael John Adams, William H. Howland, Jr., William J. Alexander
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Patent number: 6788076Abstract: An apparatus for measuring at least one electrical property of a semiconductor wafer includes a probe including a shaft having at a distal end thereof a conductive tip for electrically communicating with an object area of the semiconductor wafer. The apparatus further includes a device for applying an electrical stimulus between the conductive tip and the object area, and a device for measuring a response of the semiconductor wafer to the electrical stimulus and for determining from the response the at least one electrical property of the object area of the semiconductor wafer. A probe guard is included and surrounds the shaft of the probe adjacent the distal end of the probe. The probe guard also insulates the conductive tip from the semiconductor wafer.Type: GrantFiled: July 9, 2003Date of Patent: September 7, 2004Assignee: Solid State Measurements, Inc.Inventor: William H. Howland
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Publication number: 20040155240Abstract: An apparatus for measuring at least one electrical property of a semiconductor wafer includes a probe including a shaft having at a distal end thereof a conductive tip for electrically communicating with an object area of the semiconductor wafer. The apparatus further includes a device for applying an electrical stimulus between the conductive tip and the object area, and a device for measuring a response of the semiconductor wafer to the electrical stimulus and for determining from the response the at least one electrical property of the object area of the semiconductor wafer. A probe guard is included that surrounds the shaft of the probe adjacent the distal end of the probe. The probe guard avoids electrical communication between the probe and areas outside of the object area of the semiconductor wafer.Type: ApplicationFiled: February 10, 2003Publication date: August 12, 2004Applicant: Solid State Measurements, Inc.Inventors: William H. Howland, Robert G. Mazur
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Patent number: 6741093Abstract: A product semiconductor wafer has integrated circuits separated by scribe lines. A probe having an elastically deformable, electrically conductive tip is moved into contact with one of the scribe lines thereby forming a test structure. A suitable electrical stimulus is applied to the test structure and a response of the test structure to the electrical stimulus is measured. At least one property of the product semiconductor wafer is determined from the response.Type: GrantFiled: March 18, 2002Date of Patent: May 25, 2004Assignee: Solid State Measurements, Inc.Inventors: William H. Howland, Robert J. Hillard
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Publication number: 20030227292Abstract: A multi-probe assembly includes a chuck assembly configured to receive a back or front surface of a semiconductor wafer. A multi-probe holder has a plurality of probes each having an elastically deformable conductive tip movable into contact with a front surface of a dielectric or a front surface of a semiconducting material. A means applies an electrical stimulus to each tip, measures a response to the electrical stimulus, and determines at least one electrical property of the dielectric and/or the semiconducting material. A method for measuring at least one electrical property applies a probe (or plurality of probes) having an elastically deformable conductive tip to a scribe line(s). An electrical stimulus is applied to the probe or one of the probes with the remaining probes grounded. A response to the electrical stimulus is measured and at least one electrical property of the semiconductor wafer is determined from the response.Type: ApplicationFiled: April 11, 2002Publication date: December 11, 2003Applicant: Solid State Measurements, Inc.Inventor: William H. Howland