Patents Assigned to Solid State Measurements, Inc.
  • Patent number: 6657454
    Abstract: A method for measuring threshold voltage and average surface doping concentration of a semiconductor wafer begins by exposing a measurement site to a high intensity light immediately before a measurement sweep begins. A CV measurement sweep is made with the voltage increasing to a maximum voltage, and the response of the semiconductor wafer to CV measurement sweep is recorded. When the voltage is at the maximum voltage, the light is turned off and the capacitance of the measurement site in the absence of light is measured until the capacitance reaches equilibrium. From the recorded response, the threshold voltage and the average surface doping concentration are determined.
    Type: Grant
    Filed: March 15, 2002
    Date of Patent: December 2, 2003
    Assignee: Solid State Measurements, Inc.
    Inventor: William H. Howland
  • Publication number: 20030210066
    Abstract: An apparatus for measuring an electrical property of a semiconductor wafer includes a probe having an electrically conductive tip formed at least in part of a material that is transparent to light and a probe guard disposed adjacent the electrically conductive tip. The apparatus includes a device for selectively applying a first electrical stimulus between a semiconductor wafer and the electrically conductive tip of each probe when it is positioned in spaced relation to the semiconducting material forming the semiconductor wafer, and a device for selectively applying a second electrical stimulus between the semiconductor wafer and the probe guard of each probe. A device for measuring a response of the semiconductor wafer to the electrical stimuli and for determining from the response at least one electrical property thereof is provided. A light source can be positioned to selectively emit light through the transparent material toward the semiconductor wafer.
    Type: Application
    Filed: April 11, 2002
    Publication date: November 13, 2003
    Applicant: Solid State Measurements, Inc.
    Inventor: William H. Howland
  • Patent number: 6632691
    Abstract: An apparatus for measuring at least one electrical property of a semiconductor wafer includes a probe including a shaft having at a distal end thereof a conductive tip for electrically communicating with an object area of the semiconductor wafer. The apparatus further includes a device for applying an electrical stimulus between the conductive tip and the object area, and a device for measuring a response of the semiconductor wafer to the electrical stimulus and for determining from the response the at least one electrical property of the object area of the semiconductor wafer. A probe guard is included and surrounds the shaft of the probe adjacent the distal end of the probe. The probe guard also insulates the conductive tip from the semiconductor wafer.
    Type: Grant
    Filed: April 11, 2002
    Date of Patent: October 14, 2003
    Assignee: Solid State Measurements, Inc.
    Inventor: William H. Howland
  • Publication number: 20030071631
    Abstract: A wafer testing apparatus comprises a sample chuck having a flat surface for supporting a test wafer positioned thereon, the sample chuck having a base structure manufactured of a conductive metal and having a semiconductor layer secured to the base structure defining the flat surface of the sample chuck, an electrical test probe establishing a correction factor corresponding to a location on the semiconductor layer surface to be used to report an electrical property at a location on a test wafer substantially unaffected by the electrical properties of the semiconductor layer and base structure below that location.
    Type: Application
    Filed: August 8, 2002
    Publication date: April 17, 2003
    Applicant: Solid State Measurements, Inc.
    Inventor: William J. Alexander
  • Publication number: 20030011392
    Abstract: A sample chuck for supporting sample semiconductor wafers during testing includes an upper layer formed from a semiconducting material laminated to a lower layer formed from a conducting material.
    Type: Application
    Filed: May 3, 2002
    Publication date: January 16, 2003
    Applicant: Solid State Measurements, Inc.
    Inventors: Michael John Adams, William H. Howland, William J. Alexander
  • Patent number: 6492827
    Abstract: A semiconductor wafer probe assembly (10) includes a chuck assembly (18, 20) configured to receive a back surface (30) of a semiconductor wafer (14) and an electrical contact (20) for contacting the semiconductor wafer (14). A probe (36) having an elastically deformable conductive tip (38) is movable into contact with a semiconducting material forming a front surface (13) of the semiconductor wafer (14) or with a front surface (34) of a dielectric (12) formed on the front surface of the semiconducting material. A tester (82) is connected for applying an electrical stimulus between the electrical contact (20) and the conductive tip (38) for measuring a response to the electrical stimulus and for determining from the response at least one electrical property of the semiconducting material and/or the dielectric (12).
    Type: Grant
    Filed: October 19, 2000
    Date of Patent: December 10, 2002
    Assignee: Solid State Measurements, Inc.
    Inventors: Robert G. Mazur, Robert J. Hillard
  • Patent number: 6150832
    Abstract: An apparatus for conducting noncontact capacitance versus voltage measurements over a flat surface of a test wafer comprises a capacitance measuring head mounted on a positioning arm. The positioning arm is kinematically mounted and positions the measuring head over the test wafer. The capacitance measuring head has a plurality of electrically separate capacitor plates, one for use in making the capacitance versus voltage measurements and the remaining plates for providing capacitive position signals. Actuators responsive to the position signals place the measuring head very close to and substantially parallel to the surface of the test wafer.
    Type: Grant
    Filed: March 19, 1999
    Date of Patent: November 21, 2000
    Assignee: Solid State Measurements, Inc.
    Inventors: Robert G. Mazur, Robert J. Hillard
  • Patent number: 6052653
    Abstract: A system for automatic spreading resistance profiling of wafer specimens. The system comprises a positioning stage for positioning the specimens for contact by probe tips and alternately a probe conditioning fixture or a sample calibration fixture. The system further comprises a programmed computer for controlling the positioning stage to effect automatic specimen profiling, probe tip conditioning, and calibration.
    Type: Grant
    Filed: July 11, 1997
    Date of Patent: April 18, 2000
    Assignee: Solid State Measurements, Inc.
    Inventors: Robert G. Mazur, Robert C. Stephenson, Mark J. Andy, Catherine L. Hartford, John R. Rogers
  • Patent number: 5036271
    Abstract: An apparatus for the measurement of electrical properties of a semiconductor wafer is disclosed. A top contact mercury probe for contacting the upper surface of a wafer body is provided. The mercury probe is held by a kinematically stable probe arm which provides for very controlled movement of the mercury probe. A semiconductor wafer body horizontal and rotational movement system is provided for moving the wafer body to provide mapping capability. A top side return contact for doing measurements on wafer bodies with insulating substrates is disclosed. The top side return contact is also provided with a self-levelling and raising function, which ensures the bottom surface of the contact member to intimately contact the upper surface of the wafer body when desired, and also to raise the contact member off the wafer body when the bottom contact underneath the wafer is utilized.
    Type: Grant
    Filed: May 23, 1990
    Date of Patent: July 30, 1991
    Assignee: Solid State Measurements, Inc.
    Inventors: Robert G. Mazur, Robert C. Stephenson, Donald A. Zier, Jr.
  • Patent number: 5023561
    Abstract: An apparatus and method for measurement of electrical properties of a dielectric layer on a semiconductor wafer body is disclosed. The apparatus supports the semiconductor wafer body in position and two electrical contacts are utilized, one of which is a probe tip having a uniformly flat contact portion. Means are provided for establishing a planar contact between the flat contact portion of the probe tip and the dielectric layer of the semiconductor wafer. Measurements of the electrical properties of the dielectric layer can then be made without the use of patterned mesas.
    Type: Grant
    Filed: May 4, 1990
    Date of Patent: June 11, 1991
    Assignee: Solid State Measurements, Inc.
    Inventor: Robert J. Hillard
  • Patent number: 4489521
    Abstract: An apparatus for abrading workpieces, particularly a semiconductor wafer, includes a spinner plate having acentral support and a finger pocket at one end to rotate the plate about a collar that is affixed to the central part of an abrading plate. The spinner plate carries at its end opposite the finger pocket, a fixture used to support the workpiece for movement along a circular track on the abrading plate. The abrading plate is supported within a tray.
    Type: Grant
    Filed: June 16, 1982
    Date of Patent: December 25, 1984
    Assignee: Solid State Measurements, Inc.
    Inventor: Robert G. Mazur
  • Patent number: 4090132
    Abstract: A system is provided for measuring excess carrier lifetime in semiconductor devices. A series of rectangular current pulses is applied to the device to be tested, and the slope of the open-circuit voltage decay curve following termination of each pulse is observed. The slope of the curve is determined at a predetermined voltage level by means of voltage comparators which produce an output pulse having a width indicating the time interval required for the open-circuit voltage to decay from a preset level to a lower preset level. The excess carrier lifetime is determined from the slope of the voltage decay curve, and is visually displayed in microseconds in a digital display. Provision is also made for observing the voltage decay curve on an oscilloscope.
    Type: Grant
    Filed: March 10, 1976
    Date of Patent: May 16, 1978
    Assignee: Solid State Measurements, Inc.
    Inventor: William J. Alexander
  • Patent number: 3978622
    Abstract: Apparatus for abrading workpieces, particularly semiconductor wafers, characterized in that the workpiece is disposed on an abrading material in a lapping and polishing tray carried on a generally horizontal support plate. The plate is caused to oscillate or eccentrically rotate by a single, centrally located eccentric arm, the plate being restrained against rotary movement about the eccentric arm by resilient means which extend between stationary pins arranged around the support plate and points on the support plate intermediate the pins.
    Type: Grant
    Filed: July 23, 1975
    Date of Patent: September 7, 1976
    Assignee: Solid State Measurements, Inc.
    Inventors: Robert G. Mazur, Gilbert A. Gruber, Robert C. Stephenson