Patents Assigned to Spansion LLC
  • Publication number: 20160277184
    Abstract: A device and method for resisting, non-invasive attacks are disclosed herein. The device includes a random number generator that generates a random number, and a multiplier that multiplies first data and second data in a unit of a bit length determined based on the random number.
    Type: Application
    Filed: March 17, 2015
    Publication date: September 22, 2016
    Applicant: Spansion LLC
    Inventor: Toru Katayama
  • Publication number: 20160146675
    Abstract: A temperature detection circuit and a temperature measurement circuit capable of detecting and measuring temperatures precisely are disclosed. The temperature detection circuit includes n temperature detectors (n is an integer of 2 or more), each of the temperature detectors being configured to output a detection signal of high level when a temperature of an object reaches a first value, and a temperature determination part configured to determine whether or not the temperature of the object has reached a second value based on a count of high-level detection signals.
    Type: Application
    Filed: November 24, 2014
    Publication date: May 26, 2016
    Applicant: Spansion LLC
    Inventors: Kazuhiro KAMIYA, Kimitoshi Niratsuka
  • Publication number: 20160134103
    Abstract: A protecting circuit includes: a discharge switch configured to connect to a first terminal and a second terminal; a trigger circuit comprising load devices configured to be connected in series between the first terminal and the second terminal, each of the load devices being configured to consume power; and a shunt circuit comprising, between the trigger circuit and the first terminal or the second terminal, at least one shunt pathway configured to be capable of bypassing at least one of the load devices. The trigger circuit is configured to turn on the discharge switch when a voltage between the first terminal and the second terminal is higher than a first voltage value, and the shunt circuit is configured to electrically connect the shunt pathway when the voltage is higher than a second voltage value that is greater than the first voltage value.
    Type: Application
    Filed: November 7, 2014
    Publication date: May 12, 2016
    Applicant: Spansion LLC
    Inventor: Takashi NAMIZAKI
  • Publication number: 20160126250
    Abstract: A structure and method for providing improved and reliable charge trapping memory device are disclosed herein. A charge trapping field effect transistor (FET) comprising a semiconductor substrate, a doped region in the semiconductor substrate, and a gate structure on the semiconductor substrate and a method of fabricating the same are also discussed. The doped region comprises a first lateral dimension along a first direction. The gate structure comprises a charge trapping dielectric region and a charge trapping conductive region in contact with the charge trapping dielectric region.
    Type: Application
    Filed: October 30, 2014
    Publication date: May 5, 2016
    Applicant: Spansion LLC
    Inventors: Kuo Tung CHANG, Shenqing Fang, Timothy Thurgate
  • Publication number: 20160110282
    Abstract: An overlaid erase block (EB) mapping scheme for a flash memory provides efficient wear-leveling and reduces mount operation latency. The overlaid EB mapping scheme maps a first type of EB onto one of a plurality of physical erase blocks, in a corresponding portion of the flash memory. The first type of EB includes a plurality of pointers. The overlaid EB mapping scheme also maps each of second and third types of EBs onto one of the physical EBs that is not mapped to the first type of EB. The second type of EBs store system management information and the third type of EBs store user data. When the flash memory is started up, the overlaid EB mapping scheme scans the corresponding portion to locate the first type of EB, locates the system EBs using the pointers, and locates the data EBs using the system management information.
    Type: Application
    Filed: October 20, 2014
    Publication date: April 21, 2016
    Applicant: Spansion LLC
    Inventors: Shinsuke Okada, Hiroyuki Saito, Sunil Atri
  • Publication number: 20160111166
    Abstract: A semiconductor device includes: a plurality of memory cells; a plurality of local bit lines connected to respective memory cells of the plurality of memory cells; and a first amplifier. The first amplifier receives read data from each local bit line of the plurality of local bit lines and determines a transition speed of an output level of the first amplifier in response to receiving a combination of at least two pieces of read data. The first amplifier transfers, based on the determined transition speed, multivalued data of the read data to a read global bit line.
    Type: Application
    Filed: October 17, 2014
    Publication date: April 21, 2016
    Applicant: Spansion LLC
    Inventor: Kaoru Mori
  • Publication number: 20160103723
    Abstract: Disclosed herein are method, system and computer program product embodiments for improving the verification process of a system on chip (SoC). An embodiment operates by employing an active interconnect (AIC) between a processing subsystem (e.g., a central processing unit or CPU) and a plurality of peripherals, wherein the processing subsystem is linked to a plurality of applications via a plurality of drivers, and implementing a common set of software codes by at least one of the applications for a software development process and a hardware verification process. The AIC includes a plurality of communication protocols. During the software development process, the AIC configures at least one of the communication protocols to not enforce a timing limitation on one or more transactions between the processing subsystem and at least one of the peripherals, and a high-level programming language model is used for the peripherals.
    Type: Application
    Filed: October 14, 2014
    Publication date: April 14, 2016
    Applicant: Spansion LLC
    Inventors: Qamrul HASAN, William Chu, Lijun Pan, Hongjun Xue
  • Publication number: 20160049416
    Abstract: A polysilicon gate electrode is formed in a memory cell area, and a dummy polysilicon gate electrode is formed in a logic cell area of a silicon substrate. The dummy polysilicon gate electrode is removed and a gate insulation film and a metal gate electrode having a recess portion are formed. Further, contact holes are formed on source regions and drain regions of the memory cell area and the logic cell area. The recess portion of the metal gate electrode and the contact holes are filled with a wiring metal, substantially simultaneously, and thereafter the wiring metal is planarized by polishing.
    Type: Application
    Filed: August 13, 2014
    Publication date: February 18, 2016
    Applicant: Spansion LLC
    Inventors: Kimihiko HOSAKA, Toru Anezaki
  • Publication number: 20160036383
    Abstract: A crystal oscillation circuit is provided with a crystal oscillator, an inverter unit coupled in parallel with the crystal oscillator and including a plurality of inverters, a current supply unit that supplies current to at least a first inverter of the plurality of inverters a signal converter that supplies current to at least a last inverter of the plurality of inverters and outputs a voltage to an external circuit, and a current controller that makes the current supply unit provide current corresponding to a voltage level of the output voltage of the signal converter. The crystal oscillation circuit is capable of reducing power consumption.
    Type: Application
    Filed: July 30, 2014
    Publication date: February 4, 2016
    Applicant: Spansion LLC
    Inventors: Kimitoshi Niratsuka, Shingo Sakamoto
  • Publication number: 20160036332
    Abstract: A control apparatus, a buck-boost power supply, and a control method that can control an output part comprising two primary switches which are N-type transistors without changing the switching frequency are provided.
    Type: Application
    Filed: July 31, 2014
    Publication date: February 4, 2016
    Applicant: Spansion LLC
    Inventors: Makoto YASHIKI, Toru Miyamae
  • Publication number: 20160026593
    Abstract: Disclosed herein are system, apparatus, article of manufacture, method and/or computer program product embodiments for detecting the drift of the data valid window in a transaction. An embodiment operates by configuring a data capture range comprising data capture points, measuring values of a signal at the data capture points, and detecting the drift of the data valid window based on the values at the data capture points.
    Type: Application
    Filed: July 23, 2014
    Publication date: January 28, 2016
    Applicant: Spansion LLC
    Inventors: Kai Dieffenbach, Uwe Moslehner, Jasmin Kotoric
  • Publication number: 20150378882
    Abstract: Disclosed herein are system, apparatus, article of manufacture, method and/or computer program product embodiments for booting an application from multiple memories. An embodiment operates by executing in place from a first memory a first portion of the application, loading a second portion of the application from a second memory, and executing the second portion of the application.
    Type: Application
    Filed: June 30, 2014
    Publication date: December 31, 2015
    Applicant: Spansion LLC
    Inventors: Stephan Rosner, Qamrul Hasan, Venkat Natarajan
  • Publication number: 20150341034
    Abstract: Disclosed is an integrated circuit voltage level shifter including: a first set of pull-up transistors to selectively pull an output voltage towards a high voltage source level based on an input; a second set of pull-down transistors adapted to selectively pull the output voltage towards a lower voltage source level based on the input and a third set of transistors to limit current flow through the second set of pull-down transistors and to mitigate snapback of the second set of pull-down transistors using a bias gate voltage.
    Type: Application
    Filed: May 22, 2014
    Publication date: November 26, 2015
    Applicant: Spansion LLC
    Inventors: Roni Varkony, Yoram Betser
  • Publication number: 20150340098
    Abstract: Disclosed is a non-volatile memory (NVM) device including an array of NVM cells segmented into at least a first sector and a second sector and at least one sensing circuit to sense a state of a target NVM cell in the first sector using a reference current of the second sector received from at least a dynamic reference cell.
    Type: Application
    Filed: May 22, 2014
    Publication date: November 26, 2015
    Applicant: Spansion LLC
    Inventors: Eduardo Maayan, Yoram Betser, Alexander Kushnarenko
  • Publication number: 20150341023
    Abstract: Disclosed is a method of comparing two or more signals which may include: for each of the two or more signals, charging to a fixed voltage a compensation capacitor associated with a sense path of the signal, discharging each of the charged capacitors to a threshold voltage of a transistor in its respective sense path and integrating a discharge current from each capacitor with the signal sensed on the respective sense path.
    Type: Application
    Filed: May 22, 2014
    Publication date: November 26, 2015
    Applicant: Spansion LLC
    Inventors: Alexander Kushnarenko, Yoram Betser
  • Publication number: 20150333188
    Abstract: A semiconductor device having a substrate, a dielectric layer, a polycrystalline silicon (“poly”) resistor, a drain, and a source is disclosed. After implantation, the poly resistor may have a lateral doping profile with two peaks, one near each edge of the poly resistor, and a trough near the middle of the poly resistor. Such a doping profile can allow the poly resistor to have a resistance that is insensitive to small variations in critical dimension of the poly resistor. The resistance of the poly resistor may be determined by the doping dose of the tilted implant used to form the poly resistor. The tilted implant may be used to form the drain and the source of a transistor substantially simultaneously as forming the poly resistor.
    Type: Application
    Filed: May 15, 2014
    Publication date: November 19, 2015
    Applicant: Spansion LLC
    Inventors: Shenqing FANG, Timothy Thurgate, Kuo Tung Chang
  • Publication number: 20150262838
    Abstract: A system and method for providing electrical isolation between closely spaced devices in a high density integrated circuit (IC) are disclosed herein. An integrated circuit (IC) comprising a substrate, a first device, a second device, and a buried trench in the substrate and a method of fabricating the same are also discussed. The buried trench is positioned between first and second devices and may be filled with dielectric material. Alternatively, the buried trench contains air. A method of using Hydrogen annealing to create the buried trench is disclosed.
    Type: Application
    Filed: March 12, 2014
    Publication date: September 17, 2015
    Applicant: Spansion LLC
    Inventors: Rinji Sugino, Lei Xue, Ching-Huang Lu, Simon Chan
  • Publication number: 20150253988
    Abstract: Disclosed herein are system, apparatus, article of manufacture, method and/or computer program product embodiments for improving a read margin in non-volatile semiconductor memory device. An embodiment includes measuring an erase-time of a memory block in a memory device and associating an indicator from the plurality Of indicators for the memory block. The indicator is saved and later retrieved during a read operation.
    Type: Application
    Filed: March 6, 2014
    Publication date: September 10, 2015
    Applicant: Spansion LLC
    Inventors: Mee-Choo ONG, Wei-Kent ONG, Ogiwara YUUSUKE, Sie-Wei Henry LAU
  • Publication number: 20150255480
    Abstract: A semiconductor processing method to provide a high quality top oxide layer in charged-trapping NAND and NOR flash memory. The top oxide layer of NAND and NOR flash memory determines array device performance and reliability. The method described overcomes the corner thinning issue and the poor top oxide quality that results from the traditional oxidation approach of using pre-deposited silicon-rich nitride.
    Type: Application
    Filed: May 6, 2014
    Publication date: September 10, 2015
    Applicant: Spansion LLC
    Inventors: Tung-Sheng CHEN, Shenqing FANG, Inkuk KANG
  • Publication number: 20150242129
    Abstract: Disclosed herein are system, method, and computer program product embodiments for accessing data of a memory. A method embodiment operates by receiving one or more requests for data stored across at least a first memory area and a second memory area of a memory. The method continues with performing, by at least one processor, a wrapped read of data within a first memory area of the memory. The method then performs, by the at least one processor, a continuous read of data within a second memory area of the memory, the second memory area being adjacent to the first memory area. The continuous read starts at a first boundary of the second memory area, and is performed automatically after the wrapped read of data within the first memory area.
    Type: Application
    Filed: February 24, 2014
    Publication date: August 27, 2015
    Applicant: Spansion LLC
    Inventors: Qamrul HASAN, Shinsuke OKADA, Kiyomatsu SHOUJI, Yuichi ISE, Kai DIEFFENBACH