Abstract: An electronic structure (for example a reliability board or a cycling control module) has a body including a body portion insertable into a connector. A plurality of contact structures are provided on a side of the body portion, each contact structure comprising a first contact and a second contact spaced from the first contact, with the first and second contacts of each contact structure being aligned in the direction of insertion of the body portion into the connector. A corresponding second plurality of contact structures is provided on a side of the body portion opposite the first—mentioned side. These contacts connect with respective corresponding contacts of the connector.

Abstract: During formation of a charge trap separation in a semiconductor device, a polymer deposition is formed in a reactor using a first chemistry. In a following step, a second chemistry can be used to etch the polymer deposition in the reactor. The same or similar second chemistry can be used in a second etching step to expose a first oxide layer in each of the cells of the semiconductor device and to form a flat upper surface. This additional etch step can also be performed by the reactor, thereby reducing the number of machines required in the formation process.

Abstract: A method of reducing read errors in a non-volatile memory device that result from bit-line or word-line disturb conditions generated by erase operations includes selecting a subset of a memory array for refresh after each erase operation. A pointer to the refresh target section is updated as part of the method to direct the refresh operation to the appropriate subset of the memory array. Refresh may be performed subsequent to an erase operation or concurrently therewith. By distributing the time consumed by refresh operations over many erase operations so the relative refresh time for any one erase becomes small.

Abstract: In order to enable the optimization of a processor system without relying upon knowhow or manual labor, an apparatus includes: information obtainment unit for reading, from memory, trace information of the processor system and performance information corresponding to the trace information; information analysis unit for analyzing the trace information and the performance information so as to obtain a performance factor such as an idle time, a processing completion time of a task, or the number of interprocessor communications as a result of the analysis; and optimization method output unit for displaying and outputting a method of optimizing the system in response to a result of the analysis.

Abstract: An apparatus and method for testing is provided. An integrated circuit includes a comparison circuit that is arranged to trip based on a power supply signal reaching a trip point. The integrated circuit also includes an analog-to-digital converter that is arranged to convert the power supply signal into a digital signal. The integrated circuit also includes a storage component that stores a digital value associated with the digital signal, and provides the power supply value at an output pin of the integrated circuit. The integrated circuit includes a latch that is coupled between the analog-to-digital converter and the storage component. The latch is arranged to open when the comparison circuit trips, such that, when the comparison circuit trips, the storage component continues to store a digital value such that the digital value corresponds to the voltage associated with the power supply signal when the comparison circuit tripped.

Abstract: Embodiments of the present invention include a method for multi-chip packaging. For example, the method includes positioning a first integrated circuit (IC) on a substrate package based on a first set of reference markers in physical contact with the substrate package and confirming an alignment of the first IC based on a second set of reference markers in physical contact with the substrate package. A second IC is stacked onto first IC based on the first set of reference markers. An alignment of the second IC is confirmed based on the second set of reference markers, where the second set of reference markers is disposed at a different location on the substrate package than the first set of reference markers.

Abstract: A method and apparatus for a memory bus interface including a read data strobe. The interface includes a chip select for delivering a chip select signal that indicates when a peripheral device is activated, wherein said bus interface provides communication between a host device and said peripheral device. The interface also includes a differential clock pair for delivering a differential clock signal. A read data strobe is included in the interface for delivering a read data strobe signal from the peripheral device. The interface includes a data bus for delivering command, address, and data information. The read data strobe indicates when valid data is present on the data bus.

Abstract: A memory operate in a normal mode of operation or a testing mode of operation. In the testing mode of operation, the memory can measure various benchmarks of performance, such as read speed. The memory can perform an asynchronous read operation to read a word of electronic data that corresponds to an address or a page read operation in which multiple asynchronous read operations are performed to read multiple words of electronic data, also referred to as a page of electronic data, that correspond to multiple addresses. The memory can measure a time required, referred to as read speed, to read the word of electronic data or the multiple words of electronic data from the memory.

Abstract: An output switching circuit includes a switching circuit having a first transistor connected to a high-voltage power supply, a second transistor connected to a low-voltage power supply, and an output terminal at a connection node between the first and second transistors; a comparison unit that compares an input signal with a feedback signal obtained by feedback of an output signal of the output terminal via a low-pass filter to generate a comparison signal; and a drive pulse generating unit that generates first drive pulses for driving the first transistor and second drive pulses for driving the second transistor in accordance with the comparison signal.

Abstract: A memory device and a method of fabrication are provided. The memory device includes a semiconductor substrate and a charge trapping dielectric stack disposed over the semiconductor substrate. A gate electrode is disposed over the charge trapping dielectric stack, where the gate electrode electrically defines a channel within a portion of the semiconductor substrate. The memory device includes a pair of bitlines, where the bitlines have a lower portion and a substantially trapezoidal shaped upper portion.

Abstract: A semiconductor memory device employs a SONOS type memory architecture and includes a bit line diffusion layer in a shallow trench groove in which a conductive film is buried. This makes it possible to decrease the resistivity of the bit line diffusion layer without enlarging the area on the main surface of the semiconductor substrate, and to fabricate the semiconductor memory device having stable electric characteristics without enlarging the cell area. The bit line is formed by implanting ions into the sidewall of Si3N4.

Abstract: An assembly includes an integrated circuit, a film layer disposed over the integrated circuit and having a thickness of at least 50 microns, and a thermal neutron absorber layer comprising at least 0.5% thermal neutron absorber. The thermal neutron absorber layer can be a glass layer or can include a molding compound.

Abstract: In fabricating a memory device, a first electrode is provided. An alloy is formed thereon, and the alloy is oxidized to provide an oxide layer. A second electrode is provided on the oxide layer. In a further method of fabricating a memory device, a first electrode is provided. Oxide is provided on the first electrode, and an implantation step in undertaken to implant material in the oxide to form a layer including oxide and implanted material having an oxygen deficiency and/or defects therein. A second electrode is then formed on the layer.

Abstract: Providing for extended data retention of flash memory devices by program state rewrite is disclosed herein. By way of example, a memory cell or group of memory cells can be evaluated to determine a program state of the cell(s). If the cell(s) is in a program state, as opposed to a natural or non-programmed state, a charge level, voltage level and/or the like can be rewritten to a default level associated with the program state, without erasing the cell(s) first. Accordingly, conventional mechanisms for refreshing cell program state that require rewriting and erasing, typically degrading storage capacity of the memory cell, can be avoided. As a result, data stored in flash memory can be refreshed in a manner that mitigates loss of memory integrity, providing substantial benefits over conventional mechanisms that can degrade memory integrity at a relatively high rate.

Abstract: A bandgap voltage reference circuit comprising: a first P-N junction circuit generating a first voltage which changes according to a first characteristic; a second P-N junction circuit generating a second voltage which changes according to a second characteristic different from the first characteristic; an amplifier receiving the first and second voltages at a pair of input terminals and changing the amount of an output current provided from a high-voltage power supply to an output terminal according to a difference voltage between the first and second voltages, wherein an output voltage at the output terminal is provided to the first and second P-N junction circuits; and an output current controller causing the amplifier to provide the output current to the output terminal regardless of the difference voltage when the output voltage equals to or is smaller than a threshold voltage.

Abstract: A storage system and method for setting parameters and determining latency in a chained device system. Storage nodes store information and the storage nodes are organized in a daisy chained network. At least one of one of the storage nodes includes an upstream communication buffer. Flow of information to the storage nodes is based upon constraints of the communication buffer within the storage nodes. In one embodiment, communication between the master controller and the plurality storage nodes has a determined maximum latency.

Abstract: A controller includes a difference detector that detects a difference between a switching timing of a first channel of a switching power supply including a plurality of channels, and a switching timing of a second channel of the switching power supply, the plurality of channels being coupled in common to an input power supply and performing switching operations in response to clock signals, and a timing adjuster that, based on a detection result of the difference detector, increases a difference between a timing of a clock signal supplied to the first channel and a timing of a clock signal supplied to the second channel when the difference between the switching timing of the first channel and the switching timing of the second channel is smaller than a first value.

Abstract: A semiconductor device includes first and second resistors. The first resistor is formed in a first substrate region and coupled between a first node and an output node. The second resistor is formed in a second substrate region and coupled between the output node and a second node. The first substrate region is coupled to the first node which has a first voltage. The second node has a second voltage. The second substrate region is coupled to a voltage dividing node that is set in the first resistor.

Abstract: The present invention provides a system comprising a semiconductor device, a method of controlling the semiconductor device in the system, and a method of manufacturing the semiconductor device in the system. The semiconductor device includes: a semiconductor region located in a semiconductor layer formed on an isolating layer; an ONO film on the semiconductor region; bit lines on either side of the semiconductor region, which are located in the semiconductor layer, and are in contact with the isolating layer; a device isolating region on two different sides of the semiconductor region from the sides on which the bit lines are located, the device isolating region being in contact with the isolating layer; and a first voltage applying unit that is coupled to the semiconductor region. In this semiconductor device, the semiconductor region is surrounded by the bit lines and the device isolating region, and is electrically isolated from other semiconductor regions.

Abstract: A power control circuit includes a control circuit configured to perform a soft start operation before a power supply device performs a normal operation. The power control circuit also includes a counter circuit configured to divide a switching frequency of the power supply device in the normal operation, wherein the counter circuit measures a period of the soft start operation and when the period lasts for a set length, starts to divide the switching frequency, and wherein the power control circuit causes a comparator comprising the counter circuit to compare the frequency obtained by dividing the switching frequency with a reference frequency and corrects the switching frequency.