Patents Assigned to Spansion
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Patent number: 9081710Abstract: A method of restoring an ECC syndrome in a non-volatile memory device having memory cells arranged in a plurality of sectors within a memory cell array, the method comprising identifying a first sector including at least one page having a disabled ECC (error correction code) flag; reading the value of all data bits in said at least one page; calculating values for ECC bits in said at least one page; and writing said data bit values and said calculated ECC bit values to a second sector in the memory cell array.Type: GrantFiled: April 11, 2013Date of Patent: July 14, 2015Assignee: Spansion LLC.Inventors: Ilan Bloom, Amichai Givant, Yoav Yogev, Amit Shefi
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Publication number: 20150194537Abstract: A semiconductor device having a first gate stack on a substrate is disclosed. The first gate stack may include a first gate conductor over a first gate dielectric structure. A dielectric structure can be formed over the first gate stack and the substrate. The dielectric structure layer can include four or more layers of two or more dielectric films disposed in an alternating manner. The dielectric structure can be selectively etched to form an inter-gate dielectric structure. A second gate conductor can be formed over a second gate dielectric structure, adjacent to the inter-gate dielectric structure. A dielectric layer can be formed over the substrate, the first and second gate conductors, and the inter-gate dielectric structure. The first gate conductor may be used to make a memory gate and the second gate conductor can be used to make a select gate of a split-gate memory cell.Type: ApplicationFiled: January 7, 2014Publication date: July 9, 2015Applicant: Spansion LLCInventors: Chun CHEN, Shenqing Fang
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Publication number: 20150187891Abstract: A semiconductor device having a gate stack on a substrate is disclosed. The gate stack may include a mask layer disposed over a first gate conductor layer. The first gate conductor layer may be laterally etched beneath the mask layer to create an overhanging portion of the mask layer. A sidewall dielectric can be formed on the sidewall of the first gate conductor layer beneath the overhanging portion of the mask layer. A sidewall structure layer can be formed adjacent to the sidewall dielectric and beneath the overhanging portion of the mask layer. The mask layer can be removed. The first gate conductor layer can be used to form a memory gate and the sidewall structure layer can be used to form a select gate.Type: ApplicationFiled: December 30, 2013Publication date: July 2, 2015Applicant: Spansion LLCInventors: Rinji SUGINO, Scott BELL, Chun CHEN, Shenging FANG
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Publication number: 20150179817Abstract: Semiconductor devices and methods of producing the devices are disclosed. The devices are formed by forming a gate structure on a substrate. The gate structure includes a charge trapping dielectric formed between the substrate and a first poly layer. A top dielectric is formed over the poly layer and a sidewall dielectric is formed on a side of the poly layer. A second poly layer is formed over the gate structure such that a portion of the second poly layer includes a vertical portion that is in contact with the sidewall dielectric and a top portion that is in contact with the top dielectric. The top portion of the second poly layer can then be removed through, for instance, planarization.Type: ApplicationFiled: December 20, 2013Publication date: June 25, 2015Applicant: Spansion LLCInventors: Shenqing FANG, Chun CHEN, David MATSUMOTO, Mark T. RAMSBEY
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Publication number: 20150179656Abstract: Providing for a non-volatile semiconductor memory architecture that achieves high read performance is described herein. In one aspect, an array of memory transistors arranged electrically in serial is configured to control a gate voltage of a pass transistor. The pass transistor, in turn, enables current flow between two metal bitlines of the semiconductor memory architecture. Accordingly, a relative voltage or relative current of the two metal bitlines can be measured and utilized to determine a program or erase state of a transistor of the serial array of transistors. In a particular aspect, a transistor with small capacitance is chosen for the pass transistor, resulting in a fast correspondence of the pass transistor gate voltage/current relative to transistor array current. This can equate to fast read times for the transistor array, based on differential sensing of the two metal bitlines.Type: ApplicationFiled: December 20, 2013Publication date: June 25, 2015Applicant: Spansion LLCInventors: Hagop Nazarian, Richard Fastow, Lei Xue
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Publication number: 20150168851Abstract: Various embodiments provide for topography aware optical proximity correction that can improve depth of focus during wafer lithography. The system can determine the topography of the wafer using real process information. The topographical variations can be based on random defects or structural details. The system can divide the wafer into regions based on the topography of the regions and determine depth of focus values for each of the regions. Optical proximity correction can then be performed on each region separately, using the separate defocus values to yield an accurate, topographically aware optical proximity correction model for the wafer. For regions with varying topography, optical proximity correction can be performed for two defocus values corresponding to the high and low extremes, such that the resulting simulated contour is satisfies a predetermined criterion associated with accuracy.Type: ApplicationFiled: December 18, 2013Publication date: June 18, 2015Applicant: Spansion, LLCInventor: Xiaohai Li
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Publication number: 20150171100Abstract: A process for forming tilted edge wordline implants is disclosed. The process includes forming a first drain implant in a substrate, forming a first tilted implant in a substrate adjacent a first edge wordline to supplement said first drain implant where the first tilted implant is provided at a tilt angle from a first direction and forming a second tilted implant in the substrate adjacent a second edge wordline to supplement another first drain implant where the second tilted implant is provided at a tilt angle from a second direction. A second drain implant is formed in the substrate.Type: ApplicationFiled: December 17, 2013Publication date: June 18, 2015Applicant: Spansion LLCInventors: Timothy THURGATE, Yu SUN, Chun CHEN
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Publication number: 20150161320Abstract: A computer-implemented method is disclosed for optimizing one or more sub-resolution assist features for use in a photolithographic process. The method may include incorporating a sub-resolution assist feature within a virtual photomask. The virtual photomask may then be modeled to produce a virtual print. One or more intensity values corresponding to the sub-resolution assist feature may be collected from the virtual print. Based on the one or more intensity values, a probability of having been printed may by assigned to the sub-resolution assist feature. In an iterative process, the probability may be used to optimize at least one of a location and size of the sub-resolution assist feature.Type: ApplicationFiled: December 9, 2013Publication date: June 11, 2015Applicant: Spansion Inc.Inventor: Xiaohai Li
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Publication number: 20150162226Abstract: During formation of a charge trap separation in a semiconductor device, a polymer deposition is formed in a reactor using a first chemistry. In a following step, a second chemistry can be used to etch the polymer deposition in the reactor. The same or similar second chemistry can be used in a second etching step to expose a first oxide layer in each of the cells of the semiconductor device and to form a flat upper surface. This additional etch step can also be performed by the reactor, thereby reducing the number of machines required in the formation process.Type: ApplicationFiled: February 19, 2015Publication date: June 11, 2015Applicant: Spansion LLCInventor: Angela Tai HUI
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Publication number: 20150154953Abstract: A method, system and tangible computer readable medium for generating one or more wake-up words are provided. For example, the method can include receiving a text representation of the one or more wake-up words. A strength of the text representation of the one or more wake-up words can be determined based on one or more static measures. The method can also include receiving an audio representation of the one or more wake-up words. A strength of the audio representation of the one or more wake-up words can be determined based on one or more dynamic measures. Feedback on the one or more wake-up words is provided (e.g., to an end user) based on the strengths of the text and audio representations.Type: ApplicationFiled: December 2, 2013Publication date: June 4, 2015Applicant: Spansion LLCInventors: Ojas A. Bapat, Kenichi Kumatani
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Publication number: 20150155162Abstract: An approach is developed to use an acidic rinse to reduce charge during the lithographic process, and thereby eliminate the crystalline damage and associated yield loss associated with the accumulated charge. The crystalline damage has been found to occur for certain thicknesses of dielectric layers, and such damage is irreparable. A sparge can be used to dissolve carbon dioxide in water to provide a weak acidic rinse.Type: ApplicationFiled: December 3, 2013Publication date: June 4, 2015Applicant: Spansion LLCInventors: Daniel E. SUTTON, Christopher M. FOSTER, Kelley Kyle HIGGINS, SR., Moutasim KHOGLY, Alexander J. BIERWAG, Daniel H. WILCOX
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Publication number: 20150149696Abstract: Disclosed herein are system, method and/or computer program product embodiments for automatically resuming an irregular erasure stoppage in a sector of a memory system. An embodiment includes storing information related to any completed sub-stage of a multi stage erasure process and the corresponding memory sector address in a dedicated memory. After an irregular erasure stoppage occurs, an embodiment reads the information from the dedicated memory and resumes the erasure process of the memory sector from the last sub-stage completed.Type: ApplicationFiled: November 27, 2013Publication date: May 28, 2015Applicant: Spansion LLCInventors: Wei-Kent ONG, Mee-Choo ONG
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Publication number: 20150130430Abstract: An output switching circuit includes a switching circuit having a first transistor connected to a high-voltage power supply, a second transistor connected to a low-voltage power supply, and an output s terminal at a connection node between the first and second transistors; a comparison unit that compares an input signal with a feedback signal obtained by feedback of an output signal of the output terminal via a low-pass filter to generate a comparison signal; and a drive pulse generating unit that generates first drive pulses for driving the first transistor and second drive pulses for driving the second transistor in accordance with the comparison signal.Type: ApplicationFiled: January 16, 2015Publication date: May 14, 2015Applicant: Spansion LLCInventors: Takeshi WAKII, Akihito YOSHIOKA
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Publication number: 20150128011Abstract: Disclosed are methods for reading a set of bits from a NVM array (such as a SPI or parallel NOR NVM or otherwise) including: retrieving each of the set of bits from the NVM array substantially in parallel, applying substantially in parallel to each of the retrieved bits a segmented search, each search indexed using an order number of the respective bit being checked, and correcting a bit whose search indicates an error.Type: ApplicationFiled: November 6, 2013Publication date: May 7, 2015Applicant: Spansion LLCInventors: Amir Rochman, Kobi Danon, Avri Harush
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Patent number: 9021186Abstract: A memory system is provided. The system includes a controller that regulates read and write access to one or more FLASH memory devices that are employed for random access memory applications. A buffer component operates in conjunction with the controller to regulate read and write access to the one or more FLASH devices. Wear leveling components along with read and write processing components are provided to facilitate efficient operations of the FLASH memory devices.Type: GrantFiled: December 10, 2012Date of Patent: April 28, 2015Assignee: Spansion LLCInventor: Tzungren Tzeng
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Publication number: 20150109594Abstract: Manufacturing of semiconductor devices often involves performed photolithography to pattern and etch the various features of those devices. Such photolithography involves masking and focusing light onto a surface of the semiconductor device for exposing and etching the features of the semiconductor devices. However, due to design specifications and other causes, the semiconductor devices may not have a perfectly flat light-incident surface. Rather, some areas of the semiconductor device may be raised or lowered relative to other areas of the semiconductor device. Therefore, focusing the light on one area causes another to become unfocused. By carefully designing a photomask to cause phase shifts of the light transmitted therethrough, focus across all areas of the semiconductor device can be achieved during photolithography, which results in sharp and accurate patterns formed on the semiconductor device.Type: ApplicationFiled: October 17, 2013Publication date: April 23, 2015Applicant: Spansion LLCInventors: Gong CHEN, Frank Tsai
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Publication number: 20150108562Abstract: A three-dimensional charge trap semiconductor device is constructed with alternating insulating and gate layers stacked over a substrate. During the manufacturing process, a channel hole is formed in the stack and the gate layers are recessed from the channel hole. Using the recessed topography of the gate layers, a charge trap layer can be deposited on the sidewalls of the channel hole and etched, leaving individual discrete charge trap layer sections in each recess. Filling the channel hole with channel material effectively provides a three-dimensional semiconductor device having individual charge trap layer sections for each memory cell.Type: ApplicationFiled: October 17, 2013Publication date: April 23, 2015Applicant: Spansion LLCInventors: Chun CHEN, Kuo-Tung CHANG, Shenqing FANG
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Patent number: 9012299Abstract: In a method of fabricating a metal-insulator-metal (MIM) device, initially, a first electrode is provided. An oxide layer is provided on the first electrode, and a protective layer is provided on the oxide layer. An opening through the protective layer is provided to expose a portion of the oxide layer, and a portion of the first electrode underlying the exposed portion of the oxide layer is oxidized. A second electrode is provided in contact with the exposed portion of the oxide layer. In alternative embodiments, the initially provided oxide layer may be eliminated, and spacers of insulating material may be provided in the opening.Type: GrantFiled: August 14, 2014Date of Patent: April 21, 2015Assignee: Spansion LLCInventors: Steven Avanzino, Tzu-Ning Fang, Swaroop Kaza, Dong-Xiang Liao, Wai Lo, Christie Marrian, Sameer Haddad
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Patent number: 9015420Abstract: A method of operating a memory system is provided. The method includes a controller that regulates read and write access to one or more FLASH memory devices that are employed for random access memory applications. A buffer component operates in conjunction with the controller to regulate read and write access to the one or more FLASH devices. Wear leveling components along with read and write processing components are provided to facilitate efficient operations of the FLASH memory devices.Type: GrantFiled: May 5, 2014Date of Patent: April 21, 2015Assignee: Spansion LLCInventor: Tzungren Tzeng
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Patent number: 9012333Abstract: A method, in one embodiment, can include forming a tunnel oxide layer on a substrate. In addition, the method can include depositing via atomic layer deposition a first layer of silicon nitride over the tunnel oxide layer. Note that the first layer of silicon nitride includes a first silicon richness. The method can also include depositing via atomic layer deposition a second layer of silicon nitride over the first layer of silicon nitride. The second layer of silicon nitride includes a second silicon richness that is different than the first silicon richness.Type: GrantFiled: September 9, 2009Date of Patent: April 21, 2015Assignee: Spansion LLCInventors: Yi Ma, Shenqing Fang, Robert Ogle