Abstract: A method of forming high quality inductors and capacitors in semiconductor integrated circuits utilizes one or more sealed air-gaps in a supporting substrate under the passive devices. The process is compatible with standard silicon processing and can be implemented with high temperature processing at the beginning, middle, or end of an integrated circuit fabrication process. A one micron air-gap in a high resistivity epitaxial layer results in a parasitic capacitance equivalent to 3.9 micron thick silicon oxide or a 11 micron thick depletion layer in silicon.

Abstract: A MOS transistor including a gate electrode on a gate oxide over a channel region between a source region and a drain region also includes a shield electrode at least partially on the gate oxide adjacent to, self-aligned with, and at least partially coplanar with the gate electrode and between the gate electrode and drain region. Placing the shield electrode on the gate oxide improves the gate-drain shielding, reduces the gate-drain capacitance, Cgd, and reduces hot electron related reliability hazard.

Abstract: In an RF/microwave power amplifier comprising a linear array of MOSFET transistors in a semiconductor substrate, the transistors having gate and drain bond pads between adjacent transistors, drain to gate feedback capacitance is reduced by offsetting the drain bond pads from the gate bond pads. Bond wires to the drain bond pads extend in the offset direction from the drain bond pads, and bond wires to the gate bond pads extend from the gate bond pads in the opposite direction to reduce capacitive coupling between the bond wires and reduce the length of the bond wires.

Abstract: Gate to drain capacitance in a lateral DMOS and vertical DMOS field effect transistor is minimized by providing a conductive shield plate under the gate and between the gate and the drain of the transistor. In operation, the shield plate is preferably connected to a DC voltage potential and coupled to AC ground for RF power applications. The shield plate is readily fabricated in a conventional polysilicon gate process by adding one additional polysilicon deposition (or other suitable material), one additional mask, and one additional etch step. The shield plate can include a raised portion which provides lateral capacitive isolation between the gate and the drain. Alternatively, a shield contact can be provided above the shield plate and between the gate and drain to provide lateral isolation.

Abstract: An RF power amplifier linearization architecture contains main and auxiliary path RF amplifiers. A distortion-inverting circuit extracts the distortion component from the output signal of the main amplifier and combines it with a delayed sample of the RF input signal to drive an auxiliary path RF amplifier, via a predistorter. An output quadrature hybrid combines the output of the main and auxiliary path amplifiers. The cascading of the distortion-inverting circuit with the predistorter compensates for the non-linear behavior of the auxiliary path RF power amplifier thereby producing a composite signal at the output quadrature hybrid, in which RF carrier components from each amplifier combine constructively while distortion components cancel.

Abstract: A method of fabricating a MOSFET transistor and resulting structure having a drain-gate feedback capacitance shield formed in a recess between a gate electrode and the drain region. The shield does not overlap the gate and thereby minimizes effect on the input capacitance of the transistor. The process does not require complex or costly processing since one additional non-critical mask is required with selective etch used to create the recess.

Abstract: A digital signal processor-resident RF power amplifier performance monitor generates and updates signals for controlling each of an adaptive predistortion unit and a vector modulator of a preamplification signal processing loop, and a vector modulator of a feed-forward error extraction and reinjection loop. A performance monitoring routine subjects monitored aliased data to a window function and determines the spectrum of the data. The spectral data is applied to a sensitivity mask, which masks the data in accordance with a carrier--intermodulation distortion function associated with the operation of the amplifier. The output of the mask is processed to derive a measure of intermodulation distortion power. The intermodulation distortion power is subjected to an error minimization operator, such as a perturbational gradient search, that adjusts each of the control signals for the components of the loops, in such a manner as to maximally cancel intermodulation distortion products.

Abstract: The envelope-dependency of the distortion-introducing behavior of an RF power amplifier is used to derive a predistortion signal, that is derived from a plurality of respectively different work function representative signals. Each work function signal, in turn, is based upon the envelope of the input signal to the RF power amplifier. Prior to being combined into a predistortion control signal, each work function signal is controllably weighted in accordance with an error measurement comparison of the amplifier input signal with the amplifier output signal. The error measurement function yields a measure of the error contained in the amplifier output signal, and drives a weight adjustment control mechanism, which controllably varies a set of weights for each of in-phase and quadrature components of the respectively different signal functions, in such a manner as to minimize the measured error.

Abstract: A method of fabricating a MOSFET transistor and resulting structure having a drain-gate feedback capacitance shield formed in a recess between a gate electrode and the drain region. The shield does not overlap the gate and thereby minimizes effect on the input capacitance of the transistor. The process does not require complex or costly processing since one additional non-critical mask is required with selective etch used to create the recess.

Abstract: The breakdown voltage of a semiconductor device, such as a transistor fabricated in a device region in and abutting the surface of a semiconductor body with a field oxide surrounding the device region, is improved by etching the field oxide abutting the device region to reduce the thickness thereof to about 0.6-1.4 .mu.m and then forming a field plate in the recessed field oxide which is capacitively coupled to the underlying semiconductor body. The field plate can be floating, connected to a voltage potential, or connected to the semiconductor device.

Abstract: A power semiconductor device package in which a semiconductor chip is mounted on a ceramic platform and sealed thereon by a lid. The platform has opposing end portions which receive fasteners for directly fastening the platform and semiconductor device to a heat sink without the requirement of a separate mounting clamp. In one embodiment, metal films are provided on a surface of the platform adjacent to recesses for receiving the fasteners. The metal films function to distribute the stress of the fasteners over the surface of the end portions thereby minimizing the possibility of fracture of the ceramic platform.

Abstract: A digitally implemented, look-up table-based, predistortion and feed-forward correction signal processing mechanism compensates for distortion generated in the RF power amplifier. The input signal to the RF amplifier is stored for comparison with the measured the RF output. In each of predistortion and feed-forward signal processing paths, the magnitude of the complex waveform of the input signal is extracted to derive a read-out address to a dual-port RAM which stores weights to be multiplied by the input signal. In the predistortion signal processing path, the product is coupled to the RF power amplifier. In the feed-forward correction loop, the product is amplified by an auxiliary feed-forward RF amplifier and coupled into the amplified output signal path of the RF power amplifier.

Abstract: An RF power amplifier has an RF input port to which an RF input signal is coupled, an RF output port from which an amplified RF output signal is derived. An RF carrier cancellation combiner has a first input coupled to the RF input port and a second input coupled to the RF output port. The carrier cancellation combiner produces an RF error signal representative of RF distortion of a signal flow path through the RF amplifier between the RF input port and the RF output port. To reduce a residual carrier signal in the RF error signal, a wideband autocalibrating correlator correlates a reference signal, representative of the RF input signal, with the RF error signal, producing a control signal, which is coupled to a vector modulator to modify the signal flow path through the RF amplifier.

Abstract: A MOS transistor including a gate electrode on a gate oxide over a channel region between a source region and a drain region also includes a shield electrode at least partially on the gate oxide adjacent to, self-aligned with, and at least partially coplanar with the gate electrode and between the gate electrode and drain region. Placing the shield electrode on the gate oxide improves the gate-drain shielding, reduces the gate-drain capacitance, Cgd, and reduces hot electron related reliability hazard.

Abstract: Gate to drain capacitance in a lateral DMOS and vertical DMOS field effect transistor is minimized by providing a conductive shield plate under the gate and between the gate and the drain of the transistor. In operation, the shield plate is preferably connected to a DC voltage potential and coupled to AC ground for RF power applications. The shield plate is readily fabricated in a conventional polysilicon gate process by adding one additional polysilicon deposition (or other suitable material), one additional mask, and one additional etch step. The shield plate can include a raised portion which provides lateral capacitive isolation between the gate and the drain. Alternatively, a shield contact can be provided above the shield plate and between the gate and drain to provide lateral isolation.

Abstract: A digitally implemented, look-up table-based, predistortion and feed-forward correction signal processing mechanism compensates for distortion generated in the RF power amplifier. The input signal to the RF amplifier is stored for comparison with the measured the RF output. In each of predistortion and feed-forward signal processing paths, the magnitude of the complex waveform of the input signal is extracted to derive a read-out address to a dual-port RAM which stores weights to be multiplied by the input signal. In the predistortion signal processing path, the product is coupled to the RF power amplifier. In the feed-forward correction loop, the product is amplified by an auxiliary feed-forward RF amplifier and coupled into the amplified output signal path of the RF power amplifier.

Abstract: A linear MOSFET device includes a shield plate positioned between a drain and an overlying gate. A voltage bias is applied to the shield plate to maintain linear operation of the device for RF power amplification. An AC ground is preferably connected to the shield plate. The voltage bias can be varied for matching of parallel connected devices, for responding to peak input signals, and for temperature compensation.

Abstract: The envelope-dependency of the distortion-introducing behavior of an RF power amplifier is used to derive a predistortion signal, that is derived from a plurality of respectively different work function representative signals. Each work function signal, in turn, is based upon the envelope of the input signal to the RF power amplifier. Prior to being combined into a predistortion control signal, each work function signal is controllably weighted in accordance with an error measurement comparison of the amplifier input signal with the amplifier output signal. The error measurement function yields a measure of the error contained in the-amplifier output signal, and drives a weight adjustment control mechanism, which controllably varies a set of weights for each of in-phase and quadrature components of the respectively different signal functions, in such a manner as to minimize the measured error.

Abstract: Increased gain and improved stability are realized in using resistive emitter ballasting by including integrated capacitive elements in parallel with the resistive elements in the emitter circuit. A feature of the invention is an integrated capacitor structure having a small surface area to minimize parasitic capacitance, whereby resistor and capacitor surface areas of 100 square micrometers or less are obtained. Another feature of the invention is the use of a high dielectric material in realizing a resistor-capacitor impedance zero at a frequency much lower than the operating frequency of the transistor. For an operating frequency of 2 GHz and resistor values of 50-250 ohms, capacitance required is 3 pF or greater. Another feature of the invention is a method of fabricating the integrated resistive-capacitive element in either a low temperature process or a high temperature process which minimizes capacitor leakage when using a thin high dielectric insulative material between capacitor plates.