Abstract: A very rapidly converging adaptive filter which uses a variable scale factor for each weight of the filter. The value of the variable scale factor is chosen for each iteration and is based upon the sign changes of the incremental weight change. The variable scale factor exhibits large values when no sign changes occur and smaller values when sign changes occur. The new filter provides considerable improvement in increase of convergence rate and decrease in residual errors even in the presence of heavy noise while requiring only a modest increase in hardware.

Abstract: A compensated laser diode transmitter for high speed data transmission is provided with a pair of current switches, a novel current summing circuit and a novel current sink. The power output of the laser is sensed in real data time and employed to generate instantaneous feedback signals capable of instantaneously rebalancing and maintaining the power output of the laser diode.

Abstract: An instruction flow control system includes an instruction buffer for receiving stored program instructions. A program address generator signals the instruction buffer for fetching the instructions. A translate RAM decodes the fetched instructions and a translate map gate array generates an address to the translate RAM in response to mapped and remapped instructions being fetched from the instruction buffer. The map gate array looks at an operation code included in the instructions and determines if remapping is required. If so, an address is generated including a constant providing a block of specific addresses and a variable providing a specific address within the block. The mapped instruction includes a seven bit operation code field and, in response to a mapped instruction being fetched, all of the seven bits are mapped directly to the translate RAM address.

Abstract: A planar array of radiating elements which includes a plurality of radiating elements which are capable of operating upon electromagnetic signals of different frequency bands in a single planar array.

Abstract: An integrated-optic waveguide apparatus uses a photoelastic substrate for sensing temperature changes. Optical channels are formed in a photoelastic crystal substrate by depositing film stripes thereon to cause stress-induced changes in the relative refractive index responsive to changes in the substrate temperature. Absorption and coupling or switching of light waves between the channels provides a variable light intensity as a function of temperature. A single-mode temperature sensor of the interferometer type provides high sensitivity without requiring a secondary reference light source. Multimode temperature sensors are also described which exhibit a wide dynamic range useful up to several hundred degrees C. at a slight compromise in sensitivity.

Abstract: In order to avoid the sloshing of liquid within a container caused by movement of the container, the single bulk volume of the liquid is retained in the form of a plurality of separated mini-volumes. This is accomplished by providing a chamber formed by upper and lower plates and an interconnecting sidewall. A plurality of elongated, adjacent mini-chambers are provided within the chamber aligned in side-by-side relationship with the sidewall. The mini-chambers are formed by a honeycomb medium of acoustical material having one end sealed closed. The medium has no measurable magnetic susceptability and is formed of a paper material treated with a heat resistant phenolic resin. When placed within an insulated housing including isothermal shields, the chamber is useful in cryogenic applications such as, for example, storing liquid helium.

Abstract: A bus arbitration system comprising a plurality of bus lines and a clock which produces first and second phrases in which a drive generates a first logic state during the first phase to precharge the capacitance associated with the bus lines and generates either first or second logic state during the second phase. Also, a bus interface is described in which different types of information are transmitted during different phases.

Abstract: A timing generator and verifier is provided in which a PROM stores the timing constants that are employed by the generator. An address counter, which is driven by a clock timer, cycles through an associated portion of the PROM to provide a sequence of output signals which represent timing for a particular mode. If a different mode is selected, the address counter selects a different sequence of output bits. During Normal mode the address counter operates on a cyclic basis driven by a fixed frequency free running master clock. In Verify mode the address counter is stepped by the Host computer. The outputs of the PROM are coupled through a buffer and logic section, where the outputs may be modified before being coupled to an adder which accumulates a checksum based on the outputs of all of the bits for a particular selected timing.

Abstract: An acousto-optic spectrum analyzer in which the dynamic range is effectively extended by detecting the frequency bands wherein the photo-detectors are saturated and providing a filter to suppress those frequencies. With this pre-filter, the entire spectrum appears to be within the dynamic range of the photo detectors. The actual spectrum can be reconstructed using the response of the suppression filter and the photo detector output.

Abstract: A digital system employing adaptive voting circuitry to improve its fault-tolerance receives an input data bit from each of a number of input data sources. The adaptive voting circuitry has a separate section for each of the input devices which has a weight register that stores an initial weight value which determines the voting strength of the associated input device. The weight values are multiplexed through to a voting circuit which also receives the input data bits. If an input data bit is a logic "1" the weight value of the input data device that supplied this "1" signal is added to the weight values of all other input data devices that supplied "1" data bits. If the data bit from a particular input device is a logic "0", then its weight is added to the weight values for other input data devices which supplied logic "0'". Accumulative voting then takes place via adders in the voting circuit which determines whether the correct output bit should be a logic "1" or a logic "0".

Abstract: A method for fabricating high performance bipolar transistors using a single polycrystalline silicon layer whereby horizontally and vertically scaled base/emitter junctions are achieved. In an extrinsic base transistor, a composite sandwich of overlying layers of poly silicon, oxide and nitride are deposited over a substrate containing field oxide isolated monocrystalline transistor sites having buried subcollectors and sinker regions. The composite sandwich is thereafter selectively oxidized to define base, emitter and collector regions with the relative thickness of the composite sandwich and the grown oxide being controlled to assure proper horizontal extrinsic base to emitter spacings and shallow vertical intrinsic base to emitter junctions, upon completing subsequent implant and annealing steps. Each active transistor site is also surrounded by a ring-like, channel stopper which is physically isolated from the channel stopper of each other device.

Abstract: A Multiple Unit Adapter is disclosed which provides a high speed interface between a single Scientific Processor and a plurality of High Performance Storage Units. This Multiple Unit Adapter is required only when more than one High Performance Storage Unit is used in the data processing system. Since the Scientific Processor of the data processing system is configured with only a single High Performance Storage Unit port its design is simplified and, of course, its cost is reduced. This is especially so when the data processing system uses only a single High Performance Storage Unit. It therefore enables the data processing system to be expanded into a system having a larger memory capacity while keeping the design of the Scientific Processor constant, less complex and consequently less costly.

Abstract: Refresh memory apparatus for use in a CRT raster display system utilizes half field storage memories for ping ponging between updating and readout. In one TV mode of operation the even and odd raster lines are stored in the respective memories and in another TV mode the top and bottom halves of the frame are stored therein. The most significant bit and least significant bit of the vertical address signals are multiplexed to control the ping pong reading and writing of the memories and are multiplexed with the remainder of the address signal to provide the read and write addresses for the memories. The multiplexers are controlled in accordance with the TV mode in which the system is operating.

Abstract: A high speed, edge-triggered, set/reset flip-flop of relatively simple circuit configuration which operates on small, narrow pulses.

Abstract: A DC-to-DC power converter is constructed by coupling two parallel-connected inductors in series with a DC input power source. A communication switch is connected in series of each of the inductors. One terminal of each of these switches is connected to one terminal of the input power supply, and the other terminal of both of the switches is connected to the common side of the power supply. The commutation switches are controlled so that they have a switching duty cycle that is greater than 50%. Thus, whenever one of the switches turns off or on, the other switch will remain engaged during this switching time. As a result of this construction, the sum of the currents that flow through the inductors provides an output current to the load which has a greatly reduced ripple and a more constant output current. Also, harmonics of lesser amplitude and higher frequency content are drawn from lines, reducing the size of filter components required to reduce these input-current harmonics.

Abstract: A real time, optical processor for the detection and separation of multiple frequency hop signals and which is capable of determining both the frequency and the time of arrival for all frequencies within a specified bandwidth.

Abstract: A cathode ray beam deflection system operable in slew and random stroke and periodic raster display modes provides automatic power supply voltage switching to maintain linear operation and high efficiency. Control of automatic switching is obtained by continuously monitoring yoke voltage, yoke current, and deflection voltage, a power supply voltage being switched to a voltage of higher magnitude to provide a higher deflection rate when the yoke voltage exceeds a predetermined level at a predetermined current polarity and returned to a power supply voltage of lower magnitude when the higher deflection rate is no longer required.

Abstract: A mixer circuit wherein transistors are used to drive Schottky diodes in a star configuration in order to avoid the disadvantages of transformer coupling.

Abstract: Apparatus for the automatically controlling aircraft descent to a computed descent flight path. At any point in the descent portion of flight, a path error signal is used to compute an incremental speed command that is algebraically summed with a nominal descent speed command to cause the aircraft to converge to or maintain the computed descent path. Means are provided to rate limit the algebraic addition of the incremental speed command so that the convergence rate to the path is virtually constant for a given path error and so that the relatively short term dynamics of accelerating and decelerating the aircraft which may cause oscillatory behavior are avoided. The use of an incremental speed command permits a simplified control law over the prior art and permits the direct control of the minimum and maximum allowable speeds of the aircraft without the necessity of switching control laws or additional monitoring.

Abstract: A local store for a scientific vector processor which provides high speed access to scalar variables, parameters, temporary operands, and register save area contents of the system. Basically, the local store is a general purpose storage structure which provides access which is as fast as access to the general or vector registers of the vector processor. It is capable of being accessed either directly or indirectly via indexing. It resides in the virtual address area of the machine so that it is accessible for either reading or writing by the host programs. Because of its positioning in relation to the high performance main storage unit its size is transparent to the other programs of the system since it overflows automatically into the main storage unit. It also has multiple interfaces which provide a more simple matching of the bank widths and transfer rates of the rest of the scientific processor.