Abstract: Convergence correction for a delta-gun CRT at all locations on the CRT screen is accomplished by separately implementing the general equation for convergence in that coordinate system peculiar to each of the gun's location relative to the screen and modifying the equation coefficients in each of its four quadrants to effect convergence in that quadrant. The quadrants of each of the gun's coordinate system is the same as the quadrants of the CRT screen thereby allowing each of the coefficients to be changed or adjusted only when the terms it multiplies is zero. Complete convergence correction for the entire screen may be accomplished using only nine screen locations. A unique triangular convergence symbol corresponding to the gun locations is placed at each of these nine locations to adjust the equation coefficients, each leg of the convergence symbol being of a color which optimizes the viewability of the convergence of a particular gun.
Abstract: Deceleration control apparatus for an aircraft having an automatic altitude capture and hold system and an airspeed hold system, both systems controlled by controlling pitch attitude wherein during a descent from a higher altitude under airspeed-on-pitch control with throttle set at idle thrust, and at some existing negative altitude rate, a slower speed is commanded, a synthetic altitude based on the existing descent rate is computed and the attitude capture and hold system operation is switched into control in place of the airspeed on pitch control to cause the aircraft to flare toward the synthetic altitude. The resultant loss of airspeed, i.e., craft deceleration, during the altitude capture flare is monitored and when the commanded airspeed reduction is achieved, the airspeed-on-pitch control is resumed to thereby hold the commanded lower airspeed.
Abstract: A large capacity (8 memory banks of 524K error-corrected 36 bit words stored) high performance (latency as low as 240 nanoseconds, 12.8 gigabits/second aggregate data transfer capability with up to 11.4 gigabits/second utilized) pipelined (8 deep request pipeline) random access memory store simultaneously (to the limit of bank addressing conflicts) services intermixed requests from an internal exerciser plus ported requestors (up to 10) of plural types (3 types), which requestors are not of the same interface cycle time (30 nsec vs. 60 nsec). Furthermore, to such nonuniform interface cycle times, the bit-width of the data transfer interfaces (ports) to the requestors of plural types is also not uniform, but is actually wider (4 interface words of 36 bits each=144 bits) to faster (30 nanosecond) requestors than is that data transfer bit-width (2 interface words=72 bits) to slower (60 nsec) requestors.
Abstract: An apparatus for converting angular position to a linear voltage. A continuous element dual wiper potentiometer provides triangular waveforms 90.degree. apart to a waveform conversion circuit which generates a linear positive going ramp waveform in response to the angular position of the potentiometer wipers.
Abstract: A color cathode ray tube has raster scan color zones defined by X and Y positional signals derived from a stroke vector generator and stored in a digital memory. Raster scan and stroke vector displays are alternately presented in a hybrid display. The display face of the tube is scanned by a plurality of raster lines and a color transition point is defined by the intersection of a stroke vector with a raster line. The X and Y addresses of the intersection points define the raster line, pixel element, and color at the transition point. The system is arranged so that the X and Y addresses are provided by the stroke vector generator in synchronous relation with the color transition points, and read into memory during the stroke vector refresh period. During the raster scan refresh period, the memory contents are recalled in synchronism with the raster scan, passed through a digital to analog converter, and then applied to the display tube to provide filled-in color zones superposed on the stroke vector display.
Abstract: An apparatus for providing a signal representative of armature displacement in a magnetic bearing assembly for a magnetic suspension system, of the type having a force sensor applied in a closed loop to provide a linear response with respect to an input force command signal. Signals representative of currents applied to the magnetizing coils and of the sensed force are used to derive the armature displacement signal. The signal so derived is applied to modulate the magnetic flux and obviates the need for proximity devices for sensing armature displacement. A circuit for generating the armature displacement signal is provided.
Abstract: A discrete proportional-integral-differential controller, driven from a sampling digital error amplifier, is used to penetrate a quantized duty ratio control signal to provide dynamic output voltage regulation for switching dc-to-dc power converters. The sampling frequency of the digital PID controller is equal to the switching frequency of the power converter, so the digital controller may be used at different switching frequencies without recompensation. Digital techniques are also used to provide output current limiting, soft-start, undervoltage lockout, overvoltage shutdown, and power master-clear indications.
Abstract: A helicopter flight control system employs coupled torque limiters in the rotor cyclic pitch axis and collective pitch axis for airspeed and vertical path control, respectively. When the collective torque limit is reached, the cyclic pitch axis is automatically transferred to favor vertical path control. A synchronizer circuit is provided for assuring smooth acceleration transition to reduce accrued airspeed errors when the engine torque limit is no longer commanded.
Abstract: An economical circuit of n transistors and m resistors (n=4, m=1 for Emitter Coupled Logic (ECL); n=3, m=0 for Current Mode Logic (CML)) interconnects to a fast differential feedback latch of r transistors and s resistors (r=12, s=9 for ECl; r=7, s=3 for CML) using two levels of series gating and one current source in order to establish scan/set testability of such latch. An additional interconnected circuit of v transistors and w resistors (b=2, w-1 for ECL; v=1, w=0 for CML) further establishes either a reset or a set capability for such latch. The economical total scan/set testable latch of x transistors and y resistors (x=18, y=11 for ECL; x=11, y=3 for CML) exhibits an excellent delay-power product since a single current is selectively steered into one of four different paths, the remaining three of which paths are shut down. Use of but a single current source provides further economy of silicon implementation.
Abstract: A system for accelerating the granting of prioritized memory requests to a multi port memory system of a data processing system is disclosed. The priority requestor accelerator system detects the fact that one remaining requestor is in the priority memory system. The priority system logic is cleared out before the end of the normal requestor cycle. This allows the acceptance of a new set of requestors to be presented to the priority circuits at that time rather than waiting until presentation of the final request. Thus, the accelerator detects that the requestors from a previous requesting snap are on their last cycle. This allows a preclearance of the lower ranks as the priority circuit finishes its last cycle. The new requests are then loaded and the priority inputs are snapped shut beginning a new set of cycles. The overall operation happens as if the priority circuit is just moving from one requestor to another that is already in residence after the snap.
Abstract: An automatic flight control system that is software fault tolerant fail operational in response to a first generic failure utilizes two independent subsystems each including a dual channel flight control computer. One channel in each flight control computer includes a digital processor and the other channel includes two digital processors. Cross channel monitoring is included in each flight control computer to discern disagreements between the outputs of the channels. If disagreement occurs between one of the two processing elements in the channel including two processing elements and the processing element of the channel having one processing element, the involved processing element in the two-element channel is disabled. If both processing elements in the two element channel disagree with the processing element in the other channel, the subsystem is disabled. All of the processing elements perform identical tasks.
Abstract: A digital computer memory prefetches, or reads ahead, a next sequential, odd, address data word from a backing memory store containing all such odd address data words to a high speed buffer register simultaneously that the memory fetches the immediately preceding, even address data word from a backing memory store containing all such even address data words to that requestor-user, one of selective one(s) of a multiplicity of such requestor-users with which the memory communicates, which is addressably reading such even address data word. Selective one(s) of the requestor-users, which one(s) is (are) predominantly sequential in successive read addressings, does (do) enable such prefetching through a unique signal communicated to the memory. Remaining requestor-users do disable, via the alternative condition of the same signal, any prefetching; causing thereby no disturbance to the priorly read-ahead, odd address, data word.
Abstract: A D.C. isolation transformer consisting of a primary group of one or more flux shuttles coupled, preferably inductively coupled but alternatively capacitively or resistively coupled, to a secondary group of one or more additional flux shuttles is capable of transforming, and transmitting, power at both alternating and direct currents. A flux shuttle is a plurality, n, of Josephson junctions interconnected in parallel one to the next by like plurality minus one, n-1, of inductors. When the Josephson junctions and the inductors are equivalent within and between the flux shuttles as comprise both the primary and the secondary of the transformer then the transformer device will have a voltage gain of exactly an integer number, i.e. 2, 3, 4 etc. The transformer is preferably implemented in planar thin film technology, the Josephson junctions being created with the Selective Non-Anodizing Process (SNAP) while the inductors are superconducting stripline.
Abstract: A digital communication bus upon which arbitration is distributed in a multiplicity of communicable interconnected bus interface logics supports unique signals to each associated on user device and upon the bus. Arbitration inhibiting signals, called inhibit request signals, allow any one(s) user device(s) to inhibit the new entrance, via requests, into arbitration of all other bus interconnected bus interface logics and associated user devices. Arbitration among bus interface logics already registering requests continues in priority order. Each user device may, via a signal called retract request, deregister, or cancel, requests previously registered at the associated bus interface logics to arbitrate for ownership of the bus. Each user device may, via a signal called stop bus, cause continuous interface logics while being precluded from recognition that arbitration should ever be won.
Abstract: A power supply topology which minimizes inductance and capacitance requirements for filtering the ripple of single or multiple output switching mode power supplies. A capacitor at the input of the power supply provides continuous support for the output signal produced by the power supply.
Abstract: A dielectric trough waveguide antenna composed of a metallic guide having a dielectric substrate covering the bottom of the guide and a plurality metal radiators placed periodically on the dielectric at the dielectric-air interface provides a low loss antenna suitable for millimeter wave applications.
Abstract: Improved silicon semi-conductor device and process includes three layer sandwich passivation coating. The sandwich coating comprises first, a thin silica layer, preferably produced by oxidizing a silicon surface to the minimum thickness necessary to prevent interdiffusion of an overlying nitride layer with the silicon subsurface. The second layer of the sandwich construction is nitride and the third layer is a thicker layer of silica, preferably produced by plasma glass deposition which, together with the inner silica layer provides preselected electrical characteristics required of the composite barrier or passivation coating. This invention reduces manufacturing defects produced in conventional two layer passivation coatings, including a thicker silica inner layer, due to undercutting of the thicker silica inner layer upon etching to form terminal areas. Such undercutting is avoided by the thin silica inner layer in the present invention.
Abstract: A communication bus user design that significantly reduces the likelihood of bus disablement. Request to transmit received by a user are validated in the communications processor and by an interlock circuit. Logic signals generated in response to the two validations are coupled to an AND gate, wherefrom an enabling signal is coupled to an amplifier when the two logic signals coincide. Communications signals from the communications processor are thereafter coupled via the amplifier to the bus.
Abstract: A mechanism for controlling the attitude of a crop harvesting header mounted on a combine base unit for movement in a generally vertical direction and for rotational movement in a generally vertical plane to permit the header to follow changes in the ground contour is disclosed wherein a sensor bar is mounted on each respective side of the center line of the header to sense the location of the ground with respect to the corresponding end of the header. The header is provided with hydraulic lift cylinders and tilt cylinders to operably move the header vertically or rotationally. The control mechanism operably interconnects the sensor bars and the lift and tilt cylinders to effect movement of the header in response to a predetermined pattern of movement of the sensor bars.
Abstract: Transmitting and receiving apparatus for transmitting data includes a purged code encoder at the transmitter for encoding digital data into constant weight unbalanced codewords representative of the digital data. The constant weight unbalanced codewords containing error correction bits are preferably transmitted as balanced codewords and are decoded at the receiver employing Golay decoders or algebraic decoders to recover the original digital data without the requirement of a large number of matched filter previously employed for decoding.
December 14, 1983
Date of Patent:
September 23, 1986
Robert J. Currie, Craig K. Rushforth, John W. Zscheile, Jr.