Patents Assigned to SPTS Technologies Limited
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Patent number: 11961722Abstract: A method and apparatus are for controlling stress variation in a material layer formed via pulsed DC physical vapour deposition. The method includes the steps of providing a chamber having a target from which the material layer is formed and a substrate upon which the material layer is formable, and subsequently introducing a gas within the chamber. The method further includes generating a plasma within the chamber and applying a first magnetic field proximate the target to substantially localise the plasma adjacent the target. An RF bias is applied to the substrate to attract gas ions from the plasma toward the substrate and a second magnetic field is applied proximate the substrate to steer gas ions from the plasma to selective regions upon the material layer formed on the substrate.Type: GrantFiled: December 4, 2022Date of Patent: April 16, 2024Assignee: SPTS TECHNOLOGIES LIMITEDInventors: Anthony Wilby, Steve Burgess, Ian Moncrieff, Clive Widdicks, Scott Haymore, Rhonda Hyndman
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Patent number: 11913109Abstract: A magnet assembly is disclosed for steering ions used in the formation of a material layer upon a substrate during a pulsed DC physical vapour deposition process. Apparatus and methods are also disclosed incorporating the assembly for controlling thickness variation in a material layer formed via pulsed DC physical vapour deposition. The magnet assembly comprises a magnetic field generating arrangement for generating a magnetic field proximate the substrate and means for rotating the ion steering magnetic field generating arrangement about an axis of rotation, relative to the substrate. The magnetic field generating arrangement comprises a plurality of magnets configured to an array which extends around the axis of rotation, wherein the array of magnets are configured to generate a varying magnetic field strength along a radial direction relative to the axis of rotation.Type: GrantFiled: August 15, 2019Date of Patent: February 27, 2024Assignee: SPTS TECHNOLOGIES LIMITEDInventors: Tony Wilby, Steve Burgess, Adrian Thomas, Rhonda Hyndman, Scott Haymore, Clive Widdicks, Ian Moncrieff
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Patent number: 11894254Abstract: A substrate support includes an electrostatic chuck having an upper surface, and a cover positioned on the electrostatic chuck to cover the upper surface thereof. The cover includes a first face adjacent the upper surface of the electrostatic chuck, a second face for supporting a substrate, and one or more conduits extending through the cover to permit a cooling gas to flow from the second face to the first face. The cover is made from a dielectric material.Type: GrantFiled: September 11, 2019Date of Patent: February 6, 2024Assignee: SPTS TECHNOLOGIES LIMITEDInventor: Nicolas Launay
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Patent number: 11802341Abstract: A capacitively coupled Plasma Enhanced Chemical Vapour Deposition (PE-CVD) apparatus has a chamber, a first electrode with a substrate support positioned in the chamber, a second electrode with a gas inlet structure positioned in the chamber, and an RF power source connected to the gas inlet structure for supplying RF power thereto. The gas inlet structure has an edge region, a central region which depends downwardly with respect to the edge region, and one or more precursor gas inlets for introducing a PE-CVD precursor gas mixture to the chamber. The edge region and the central region both constitute part of the second electrode. The precursor gas inlets are disposed in the edge region and the central region is spaced apart from the substrate support to define a plasma dark space channel.Type: GrantFiled: January 8, 2021Date of Patent: October 31, 2023Assignee: SPTS Technologies LimitedInventors: Stephen Burgess, Kathrine Crook, Daniel Archard, William Royle, Euan Alasdair Morrison
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Patent number: 11718908Abstract: A method of depositing a film on a substrate is provided. The method includes positioning the substrate on a substrate support in a chamber and depositing the film on the substrate using a DC magnetron sputtering process in which an electrical bias signal causes ions to bombard the substrate. The substrate support includes a central region surrounded by an edge region, the central region being raised with respect to the edge region, and the substrate is positioned on the central region so that a portion of the substrate overlays the edge region and is spaced apart therefrom.Type: GrantFiled: April 27, 2021Date of Patent: August 8, 2023Assignee: SPTS TECHNOLOGIES LIMITEDInventors: Scott Haymore, Amit Rastogi, Rhonda Hyndman, Steve Burgess, Ian Moncrieff
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Patent number: 11710670Abstract: A white light illumination source can illuminate a region of a substrate to be plasma etched with an incident light beam. A camera takes successive images of the region being illuminated during a plasma etch process. Image processing techniques can be applied to the images so as to identify a location of at least one feature on the substrate and to measure a reflectivity signal at the location. The plasma etch process can be modified in response to the measured reflectivity signal at the location.Type: GrantFiled: August 21, 2020Date of Patent: July 25, 2023Assignee: SPTS Technologies LimitedInventors: Oliver Ansell, Harry Gordon-Moys
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Patent number: 11664232Abstract: A structure comprising a substrate and a component which forms involatile metal etch products is plasma etched. A structure comprising a substrate and a component which forms involatile metal etch products is provided. The structure is positioned on a support within a chamber having a first gas inlet arrangement comprising one or more gas inlets and a second gas inlet arrangement comprising one or more gas inlets. The structure is etched by performing a first plasma etch step using a first etch process gas mixture which is only introduced into the chamber through the first gas inlet arrangement. The structure is further etched by performing a second plasma etch step using a second etch process gas mixture which is only introduced into the chamber through the second gas inlet arrangement.Type: GrantFiled: November 15, 2020Date of Patent: May 30, 2023Assignee: SPTS Technologies LimitedInventors: Huma Ashraf, Kevin Riddell, Codrin Prahoveanu
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Patent number: 11643744Abstract: A method of processing a semiconductor wafer is provided. The method includes introducing the wafer to a main chamber via a loading port, using a transfer mechanism to transfer the wafer to a first wafer processing module in a stack so that the wafer is disposed substantially horizontally in the first wafer processing module with a front face facing upwards, and performing a processing step on the front face of the wafer in the first wafer processing module.Type: GrantFiled: June 24, 2021Date of Patent: May 9, 2023Assignee: SPTS TECHNOLOGIES LIMITEDInventors: John MacNeil, Martin Ayres, Trevor Thomas
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Patent number: 11545394Abstract: A semiconductor wafer dicing process is disclosed for dicing a wafer into individual dies. Scribe lines are formed within a polymer coating to expose regions of wafer to form a pre-processed product. The pre-processed product within the chamber is plasma etched to remove the exposed regions of the wafer to separate the individual dies and form a processed product. A frame cover is then removed and the processed product, wafer frame and adhesive tape are exposed to an oxygen plasma within the chamber to partially remove an outermost region of the polymer coating, which is most heavily contaminated with fluorine, to leave a residual polymer coating on the individual dies and form a post-processed product. The residual polymer coating on the individual dies of the post-processed product is then removed.Type: GrantFiled: November 10, 2020Date of Patent: January 3, 2023Assignee: SPTS Technologies LimitedInventors: Matthew Michael Day, Samira Binte Kazemi
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Patent number: 11521840Abstract: A method and apparatus are for controlling stress variation in a material layer formed via pulsed DC physical vapour deposition. The method includes the steps of providing a chamber having a target from which the material layer is formed and a substrate upon which the material layer is formable, and subsequently introducing a gas within the chamber. The method further includes generating a plasma within the chamber and applying a first magnetic field proximate the target to substantially localise the plasma adjacent the target. An RF bias is applied to the substrate to attract gas ions from the plasma toward the substrate and a second magnetic field is applied proximate the substrate to steer gas ions from the plasma to selective regions upon the material layer formed on the substrate.Type: GrantFiled: February 20, 2018Date of Patent: December 6, 2022Assignee: SPTS Technologies LimitedInventors: Anthony Wilby, Steve Burgess, Ian Moncrieff, Clive Widdicks, Scott Haymore, Rhonda Hyndman
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Patent number: 11489106Abstract: A structure comprising a semiconductor substrate and a layer of PZT (lead zirconate titanate) is etched by performing a first plasma etch step with a first etch process gas mixture. The first etch process gas mixture comprises at least one fluorine containing species. The first plasma etch step is performed so that involatile metal etch products are deposited onto interior surfaces of the chamber. The structure is further etched by performing a second plasma etch step with a second etch process gas mixture. The second etch process gas mixture comprises at least one fluorocarbon species. The second plasma etch step is performed so that a fluorocarbon polymer layer is deposited onto interior surfaces of the chamber to overlay involatile metal etch products deposited in the first plasma etch step and to provide a substrate on which further involatile metal etch products can be deposited.Type: GrantFiled: November 23, 2020Date of Patent: November 1, 2022Assignee: SPTS Technologies LimitedInventors: Huma Ashraf, Kevin Riddell, Codrin Prahoveanu
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Patent number: 11361975Abstract: A method of fabricating an integrated circuit is disclosed. The method of removing excess metal of a metal interconnection layer during integrated circuit fabrication process comprises the steps of: plasma etching an excess metal portion of the metal interconnection layer using plasma comprising a noble gas, for an etch duration. The method further comprises stopping the etch process prior to the excess metal portion being completely removed and thus prior to a dielectric surface upon which the metal interconnection is formed, becoming completely exposed. The remaining excess metal portion comprising excess metal residues is subsequently removed using a second etch step.Type: GrantFiled: October 14, 2019Date of Patent: June 14, 2022Assignee: SPTS Technologies LimitedInventors: Tony Wilby, Steve Burgess
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Patent number: 11309198Abstract: A wafer processing system has a transport vacuum chamber for handling a frame assembly under vacuum conditions, at least one vacuum cassette elevator load lock for housing a cassette and adjusting a vertical position of the cassette under vacuum conditions, and at least one wafer processing module in vacuum communication with the transport vacuum chamber. An actuating assembly changes guide members from an expanded configuration to a contracted configuration to reduce a first cross-sectional dimension of a frame assembly receiving area and to reduce a second cross-sectional dimension of the frame assembly receiving area that is perpendicular to the first cross-sectional dimension.Type: GrantFiled: July 2, 2020Date of Patent: April 19, 2022Assignee: SPTS Technologies LimitedInventors: Attila Nagy, Kris Martin
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Patent number: 11251037Abstract: A method is for depositing silicon nitride by plasma-enhanced chemical vapour deposition (PECVD). The method includes providing a PECVD apparatus including a chamber and a substrate support disposed within the chamber, positioning a substrate on the substrate support, introducing a nitrogen gas (N2) precursor into the chamber, applying a high frequency (HF) RF power and a low frequency (LF) RF power to sustain a plasma in the chamber, introducing a silane precursor into the chamber while the HF and LF RF powers are being applied so that the silane precursor forms part of the plasma being sustained, and subsequently removing the LF RF power or reducing the LF RF power by at least 90% while continuing to sustain the plasma so that silicon nitride is deposited onto the substrate by PECVD.Type: GrantFiled: August 15, 2019Date of Patent: February 15, 2022Assignee: SPTS TECHNOLOGIES LIMITEDInventors: Kathrine Crook, Steve Burgess
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Patent number: 11236433Abstract: An apparatus for electrochemically processing a semiconductor substrate includes a processing chamber of the type that is sealable to a peripheral portion of a semiconductor substrate so as to define a covered processing volume. The semiconductor substrate is supported by a substrate support. A magnetic arrangement is disposed outside of the processing chamber and produces a magnetic field. The magnetic field is changed using a controller for controlling the magnetic arrangement. An agitator is disposed within the processing chamber. The agitator comprises a magnetically responsive element which is responsive to changes in the magnetic field of the magnetic arrangement so as to provide a reciprocating motion to the agitator.Type: GrantFiled: April 10, 2020Date of Patent: February 1, 2022Assignee: SPTS Technologies LimitedInventors: Martin Ayres, John MacNeil, Trevor Thomas
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Patent number: 11217442Abstract: A method of depositing a SiN film onto a flexible substrate includes providing the flexible substrate, and depositing the SiN film onto the flexible substrate in a plasma enhanced chemical vapour deposition (PECVD) process using SiH4, N2 and H2, in which the temperature of the substrate is 200° C. or less and SiH4 is introduced into the PECVD process at a flow rate of greater than 100 sccm.Type: GrantFiled: April 25, 2019Date of Patent: January 4, 2022Assignee: SPTS TECHNOLOGIES LIMITEDInventor: Mark Carruthers
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Patent number: 11189463Abstract: A plasma generating arrangement includes a plurality of plasma sources, each plasma source including a respective antenna coil assembly electrically coupled to a common electrical terminal via a respective transmission line. Each transmission line is configured to communicate a radio frequency electrical power signal from the common electrical terminal to the respective antenna coil assembly, and has a length which is an odd multiple of ¼ of the wavelength of the radio frequency electrical power signal.Type: GrantFiled: February 25, 2019Date of Patent: November 30, 2021Assignee: SPTS TECHNOLOGIES LIMITEDInventor: Paul Bennett
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Patent number: 11127568Abstract: A method is for cleaning a plasma etching apparatus of the type used to etch a substrate and having at least one chamber. The method includes sputtering a metallic material from an electrically conductive coil which is positioned within the at least one chamber onto an interior surface of the at least one chamber to perform a cleaning function.Type: GrantFiled: May 21, 2019Date of Patent: September 21, 2021Assignee: SPTS Technologies LimitedInventors: Stephen R. Burgess, Anthony Paul Wilby
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Patent number: 11066754Abstract: An apparatus for processing a front face of a semiconductor wafer is provided. The apparatus includes a main chamber, at least one loading port connected to the main chamber for introducing the wafer to the main chamber, at least one stack of wafer processing modules, and a transfer mechanism for transferring the wafer between the loading port and the processing modules. The at least one stack of wafer processing modules includes three or more substantially vertically stacked wafer processing modules, wherein adjacent wafer processing modules in the stack have a vertical separation of less than 50 cm, and each processing module is configured to process the wafer when disposed substantially horizontally therein with the front face of the wafer facing upwards, and at least one wafer processing module is an electrochemical wafer processing module.Type: GrantFiled: January 22, 2018Date of Patent: July 20, 2021Assignee: SPTS Technologies LimitedInventors: John Macneil, Martin Ayres, Trevor Thomas
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Patent number: 11037793Abstract: According to the invention there is provided a method of plasma etching a silicon-based compound semiconductor substrate, the method comprising providing the substrate within an etch chamber and performing a cyclical process on the substrate, each cycle comprising supplying an etchant gas into the chamber, energising the gas into a plasma, and performing an etch step on the substrate using the plasma; and performing a desorption step, wherein during the desorption step, the only gas that is supplied into the etch chamber is an inert gas, so as to allow reactive species that have adsorbed to the surface of the substrate during the etch step to desorb from the surface of the substrate.Type: GrantFiled: June 20, 2019Date of Patent: June 15, 2021Assignee: SPTS Technologies LimitedInventors: Huma Ashraf, Kevin Riddell, Alex Wood