Patents Assigned to STMicroelectronics (Rousset) SAS
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Patent number: 12368433Abstract: An electronic system is configured to generate a sequential logic signal. The electronic system includes a first ring oscillator including a first plurality of cascaded inverter stages. A combinational logic circuit is configured to generate the sequential logic signal by combining signals at the output terminals of at least two of the inverter stages of the first ring oscillator. The electronic system further includes a second ring oscillator including a second plurality of cascaded inverter stages. A bias current source is configured to supply the inverter stages of the second ring oscillator with a bias current, and a first voltage is generated at the inverter stages of the second ring oscillator. A voltage follower is configured to supply the inverter stages of the first ring oscillator with a second voltage corresponding to the first voltage generated at the inverter stages of the second ring oscillator.Type: GrantFiled: August 17, 2023Date of Patent: July 22, 2025Assignee: STMicroelectronics S.r.l.Inventors: Pietro Antonino Coppa, Gianbattista Lo Giudice, Enrico Castaldo, Antonino Conte
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Patent number: 12366973Abstract: According to an embodiment, a method includes adjusting a reference generator into a first configuration based on a temporary trim value resulting, in a first reference voltage and a first reference current being generated for a first memory. The method further includes performing an integrity check on an initial set of data downloaded from the first memory based on the first reference voltage and the first reference current. The initial set of data includes a first trim value. The method further includes downloading contents from the first memory into a second memory in response to a successful integrity check after adjusting the reference generator into a second configuration. In the second configuration, the reference generator generates a second reference voltage and a second reference current for the first memory. The reference generator is adjusted by the first trim value in response to a successful integrity check.Type: GrantFiled: January 18, 2024Date of Patent: July 22, 2025Assignee: STMicroelectronics International N.V.Inventors: Naren Kumar Sahoo, Pavan Nallamothu, Christiana Kapatsori, Yamu Hu, David McClure
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Patent number: 12366605Abstract: According to an embodiment, a digital circuit includes an OR gate and a flip-flop. The OR gate includes a first input and a second input. The first input of the OR gate is coupled to a control signal, and the second input of the OR gate is coupled to an uncovered functional combination logic of the digital circuit. The first input of the OR gate is configured to be pulled low by the control signal in response to setting the digital circuit in a configuration to test the uncovered functional combination logic. The flip-flop includes a reset pin or a set pin coupled to the output of the OR gate. The output of the flip-flop is configured to be observed during a testing of the uncovered functional combination logic to detect defects in the digital circuit.Type: GrantFiled: January 24, 2023Date of Patent: July 22, 2025Assignee: STMicroelectronics International N.V.Inventors: Venkata Narayanan Srinivasan, Umesh Chandra Srivastava, Shiv Kumar Vats, Manish Sharma
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Patent number: 12368376Abstract: In an embodiment, a voltage multiplier comprises an input node, an output node, and first and second control nodes for receiving first and second clock signals defining two commutation states. An ordered sequence of intermediate nodes is coupled between the input and output nodes and includes two ordered sub-sequences. Capacitors are coupled: between each odd intermediate node in the first sub-sequence and the first control node; between each even intermediate node in the first sub-sequence and the second control node; between each odd intermediate node in the second sub-sequence and a corresponding odd intermediate node in the first sub-sequence; and between each even intermediate node in the second sub-sequence and a corresponding even intermediate node in the first sub-sequence. The circuit comprises selectively conductive electronic components coupled to the intermediate nodes.Type: GrantFiled: February 5, 2024Date of Patent: July 22, 2025Assignee: STMicroelectronics S.r.l.Inventor: Francesco Pulvirenti
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Publication number: 20250233557Abstract: An electronic frequency mixer includes at least one transistor having a front gate, a back gate, a source, and a drain. The source is coupled to a node of application of a radio frequency input signal. The front gate is coupled to a node of application of a first periodic signal at a first frequency. The back gate is coupled to one of: a node of application of the first periodic signal or a node of application of a second periodic signal at the first frequency.Type: ApplicationFiled: January 14, 2025Publication date: July 17, 2025Applicant: STMicroelectronics International N.V.Inventor: Valerie DANELON
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Publication number: 20250231216Abstract: The present disclosure is directed to shock and orientation detection for an electronic device. The shock detection detects shock events, such as an accidental drop of the device, and the orientation detection detects the orientation of the device at the time of the detected shock event. The detected shock event and orientations are stored in non-volatile memory. The shock and orientation detection are implemented in low power hardware without any host intervention, and may be implemented as an always-on feature that executes even when the device is in an off or low power state.Type: ApplicationFiled: January 11, 2024Publication date: July 17, 2025Applicant: STMicroelectronics International N.V.Inventors: Stefano Paolo RIVOLTA, Piergiorgio ARRIGONI
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Patent number: 12361268Abstract: A convolutional neural network includes convolution circuitry. The convolution circuitry performs convolution operations on input tensor values. The convolutional neural network includes requantization circuitry that requantizes convolution values output from the convolution circuitry.Type: GrantFiled: August 30, 2021Date of Patent: July 15, 2025Assignee: STMicroelectronics International N.V.Inventors: Giuseppe Desoli, Surinder Pal Singh, Thomas Boesch
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Patent number: 12360684Abstract: In accordance with an embodiment, a system-on-chip includes: a memory circuit comprising a first memory region accessible with a first access right level and a second memory region accessible with the first access right level or a second access right level, at least one first peripheral having the first access right level, at least one second peripheral having the second access right level; and a direct memory access circuit configured to generate direct memory accesses, wherein the direct memory access circuit includes at least one first direct memory access controller having the first access right level and at least one second direct memory access controller having the second access right level.Type: GrantFiled: March 29, 2023Date of Patent: July 15, 2025Assignee: STMicroelectronics (Rousset) SASInventors: Mark Wallis, Laurent Lestringand
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Patent number: 12360546Abstract: A method for regulating voltage in an electronic device includes receiving, at a power stage, a gate voltage from an input terminal, and delivering an output voltage and an output current to a processing module based on the gate voltage. The gate voltage is compensated by comparing the output voltage with a reference voltage to produce a compensated gate voltage. The gate voltage compensation is sped by up stabilizing the output voltage during transitions between operational modes using a first compensation stage, decoupling a second compensation stage from the input terminal when a control signal is asserted to thereby precharge a compensation capacitor to an initial compensation voltage, and coupling the second compensation stage to the input terminal via a compensation resistor when the control signal is deasserted to thereby deliver the initial compensation voltage to the input terminal.Type: GrantFiled: December 6, 2023Date of Patent: July 15, 2025Assignee: STMicroelectronics FranceInventors: Lionel Vogt, Eoin Padraig O Hannaidh
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Patent number: 12362735Abstract: A controller for an electronic circuit that includes a first and a second switch is provided. The controller includes an event detector stage that receives logic electrical signals and a pulse generator circuit, which is coupled to the event detector stage and generates a dead time signal based on edges of the logic electrical signals detected by the event detector stage. The dead time signal includes pulses delimited by an edge of a first type and by a subsequent edge of a second type. A combinatorial sampling circuit generates a first and a second sampled preliminary signal. An update stage updates the values of the first and the second control signals at each pulse of the dead time signal based on the first and the second sampled preliminary signals, subsequently to the edge of the first type or the second type of the pulse of the dead time signal.Type: GrantFiled: August 17, 2023Date of Patent: July 15, 2025Assignee: STMicroelectronics S.r.l.Inventors: Ivan Floriani, Elena Brigo
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Patent number: 12360296Abstract: Methods of manufacture of an optical diffuser. In one embodiment, an optical diffuser is formed by providing a wafer including a silicon slice of which an upper face is covered with a first layer made of a first material itself covered with a second layer made of a second selectively etchable material with respect to the first material. The method further includes forming openings in the second layer extending up to the first layer and filling the openings in the second layer with a third material. The method yet further includes bonding a glass substrate to the wafer on the side of its upper face and removing the silicon slice.Type: GrantFiled: July 28, 2023Date of Patent: July 15, 2025Assignee: STMicroelectronics (Crolles 2) SASInventors: Vincent Farys, Alain Inard, Olivier Noblanc
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Patent number: 12363932Abstract: The disclosure concerns an electronic device comprising, stacked from a first surface to a second surface, a first stack and a second stack of two high electron mobility transistors, referred to as first and second transistor, the first and the second stack each comprising, from an insulating layer, interposed between the first and the second stack, a barrier layer and a channel layer, the first and the second transistor respectively comprising a first and a second set of electrodes, the first and the second set of electrodes being each provided with a source electrode, with a drain electrode, and with a gate electrode which are arranged so that the first and the second transistor form a half-arm of a bridge.Type: GrantFiled: May 4, 2022Date of Patent: July 15, 2025Assignees: STMicroelectronics France, STMicroelectronics International N.V.Inventors: Matthieu Nongaillard, Thomas Oheix
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Patent number: 12362734Abstract: A circuit includes a clock input node, a first signal input node configured to receive a first modulated signal switching between a first DC voltage and a second DC voltage, a bias circuit, a first output node, a first capacitor, a second capacitor, and switching circuitry coupled to the first capacitor and the second capacitor. Control circuitry is configured to initially set the switching circuitry in a first configuration in response to the first modulated signal having the second DC voltage, thereby charging the first capacitor to the second DC voltage and charging the second capacitor to the first DC voltage, and subsequently set the switching circuitry in a second configuration in response to an edge detected in the clock signal, thereby producing the first threshold voltage at the first output node after charge redistribution taking place between the first and second capacitors.Type: GrantFiled: July 26, 2023Date of Patent: July 15, 2025Assignees: STMicroelectronics S.r.l., Alma Mater Studiorum—Universita' Di BolognaInventors: Matteo D'Addato, Alessia Maria Elgani, Luca Perilli, Eleonora Franchi Scarselli, Antonio Gnudi, Roberto Antonio Canegallo, Giulio Ricotti
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Publication number: 20250226304Abstract: A first layer of a resin compatible with a laser direct structuring (LDS) is formed on a substrate and encapsulates a first integrated circuit. The substrate includes a first connection terminal electrically coupled to the first integrated circuit and a second connection terminal covered by the first layer. A first via is formed using LDS, the first via crossing the first layer and forming an electrical connection to the second connection terminal. A second integrated circuit is mounted over the first integrated circuit. A second layer of resin compatible with LDS is formed to encapsulate the second integrated circuit. A second via is formed using LDS, the second via crossing the second layer and forming an electrical connection to the first via.Type: ApplicationFiled: January 8, 2025Publication date: July 10, 2025Applicant: STMicroelectronics International N.V.Inventor: Romain COFFY
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Patent number: 12356743Abstract: Disclosed herein is a method of reducing noise captured by an image sensor. The method includes affixing a bottom surface of a glass covering to the image sensor, permitting light to impinge upon the glass covering, and shaping the glass covering such that when the light that impinges upon the glass covering impinges upon a sidewall of the glass covering, the sidewall reflects the light on a trajectory away from the image sensor.Type: GrantFiled: February 21, 2024Date of Patent: July 8, 2025Assignee: STMicroelectronics PTE LTDInventors: Laurent Herard, David Gani
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Patent number: 12353880Abstract: In an embodiment a One-Time Programmable (OTP) memory controller includes a data register, a given number K of shadow-registers, wherein the number K is smaller than a given number N of memory slots of an OTP memory area, a communication interface configured to receive a read request requesting the data of a given memory slot and a control circuit configured to receive a preload start signal and a shadow-register preload enable signal, wherein the control circuit is configured to manage a preload phase and a data-read phase.Type: GrantFiled: May 30, 2023Date of Patent: July 8, 2025Assignee: STMicroelectronics S.r.l.Inventors: Antonino Giuseppe Fontana, Giuseppe Guarnaccia, Stefano Catalano
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Patent number: 12356101Abstract: An image sensor includes an array of pixels inside and on top of a substrate. A control circuit is configured to apply voltage potentials to the substrate. During a first phase, the control circuit applies a ground potential to the substrate. During a second phase, the control circuit applies a potential positive with respect to the ground potential to the substrate.Type: GrantFiled: August 11, 2022Date of Patent: July 8, 2025Assignees: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics (Crolles 2) SASInventors: Laurent Simony, Frederic Lalanne
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Patent number: 12354886Abstract: One or more semiconductor dice are arranged on a substrate. The semiconductor die or dice have a first surface adjacent the substrate and a second surface facing away from the substrate. Laser-induced forward transfer (LIFT) processing is applied to the semiconductor die or dice to form fiducial markers on the second surface of the semiconductor die or dice. Laser direct structuring (LDS) material is molded onto the substrate. The fiducial markers on the second surface of the semiconductor die or dice are optically detectable at the surface of the LDS material. Laser beam processing is applied to the molded LDS material at spatial positions located as a function of the optically detected fiducial markers to provide electrically conductive formations for the semiconductor die or dice.Type: GrantFiled: May 24, 2022Date of Patent: July 8, 2025Assignee: STMicroelectronics S.r.l.Inventor: Andrea Albertinetti
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Patent number: 12353341Abstract: A memory circuit includes an array of memory cells arranged in rows and columns. A word line is connected to the memory cells of each row. A row decoder circuit operates in response to an internal clock and an address to selectively apply a word line signal to one word line and further generate a dummy word line signal. A control circuit includes a clock generator that generates the internal clock which is reset in response to a reset signal. A first delay circuit receives the dummy word line signal and outputs a first delayed dummy word line signal. A second delay circuit receives the dummy word line signal and outputs a second delayed dummy word line signal. A multiplexer circuit selects between the first and second delayed dummy word line signals for output as the reset signal in response to a logic state of a mode control signal.Type: GrantFiled: October 12, 2023Date of Patent: July 8, 2025Assignee: STMicroelectronics International N.V.Inventors: Bhupender Singh, Hitesh Chawla, Tanuj Kumar, Harsh Rawat, Kedar Janardan Dhori, Promod Kumar, Manuj Ayodhyawasi, Nitin Chawla
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Patent number: 12353538Abstract: In an embodiment a method includes compiling, by a processor in a compiling phase, a software program intended to be executed by the processor, the processor having secure and non-secure access right level execution contexts, and/or privileged and non-privileged access right level execution contexts and generating, in the compilation phase, instructions in machine language having an exclusively secure access right level when the instructions are intended to be executed in the secure access right level execution context, and instructions having a non-privileged access right level when the instructions are intended to be executed in the non-privileged access right level execution context.Type: GrantFiled: November 22, 2022Date of Patent: July 8, 2025Assignee: STMicroelectronics (Grand Ouest) SASInventors: Michel Jaouen, Loic Pallardy, Ludovic Barre