Abstract: A memory circuit includes an array of memory cells arranged in rows and columns. A word line is connected to the memory cells of each row. A row decoder circuit operates in response to an internal clock and an address to selectively apply a word line signal to one word line and further generate a dummy word line signal. A control circuit includes a clock generator that generates the internal clock which is reset in response to a reset signal. A first delay circuit receives the dummy word line signal and outputs a first delayed dummy word line signal. A second delay circuit receives the dummy word line signal and outputs a second delayed dummy word line signal. A multiplexer circuit selects between the first and second delayed dummy word line signals for output as the reset signal in response to a logic state of a mode control signal.

Abstract: The integrated circuit includes a logic part including standard cells arranged in parallel rows along a first direction and in an alternation of complementary semiconductor wells. Among the standard cells, at least one capacitive filling structure belongs to two adjacent rows and includes a capacitive interface between a conductive armature and the first well, the extent of the second well in the first direction being interrupted over the length of the capacitive filling structure so that the first well occupies in the second direction the width of the two adjacent rows of the capacitive filling structure. A conductive structure electrically connects the second well on either side of the capacitive filling structure.

Abstract: A support substrate supports an electronic chip. An encapsulation coating on the support substrate coats the electronic chip. The encapsulation coating includes a trench surrounding the electronic chip. A heat sink is mounted to the encapsulation coating above the electronic chip. The heat sink is fixed to the encapsulation coating by an adhesive material and a thermal interface material layer is present between the electronic chip and the heat sink. The trench is positioned between the thermal interface material layer and the adhesive material.

Abstract: A cryptographic operation is protected. The protecting includes performing a matrix transformation operation on a matrix having n rows and n columns, each row forming a respective vector of a first set of ordered vectors. A second set of ordered vectors is generated by shifting values of vectors of the first set of ordered vectors in a first direction, wherein a pitch of a shift applied to a vector of the first set of ordered vectors is based on an order number of the vector of the first set of ordered vectors. A working vector is generated by logically combining vectors of the second set of ordered vectors. A third set of ordered vectors is generated based on the second set of ordered vectors. A fourth set of ordered vectors is generated based on the third set of ordered vectors and the working vector.

Abstract: An electronic device includes—a semiconductor substrate having selection transistors arranged therein and a first interconnection stack including at least one level including first and second insulating layers having conductive tracks and first conductive vias defined therein. The electronic device includes a third insulating layer on the first stack and a second interconnection stack including at least one level including first and second insulating layers. The electronic device includes a plurality of memory cells arranged in the third insulating layer and at least one second conductive via extending through the entire height of the third insulating layer.

Abstract: The present disclosure relates to a method for forming a cavity that traverses a stack of layers including a bottom layer, a first portion of which locally presents an excess thickness, the method comprising a first step of non-selective etching and a second step of selective etching vertically in line with the first portion.

Abstract: In an embodiment, a method includes: receiving a first plurality of digital codes from a time-to-digital converter (TDC); generating a coarse histogram from the first plurality of digital codes; detecting a peak coarse bin from the plurality of coarse bins; after receiving the first plurality of digital codes, receiving a second plurality of digital codes from the TDC; and generating a fine histogram from the second plurality of digital codes based on the detected peak coarse bin, where a fine histogram depth range is narrower than a coarse histogram depth range, where a lowest fine histogram depth is lower or equal to a lowest coarse peak depth, and where a highest fine histogram depth is higher or equal to a highest coarse peak depth.

Abstract: A device and method of manufacturing a device based on heterostructure, including a work body, is provided having a wafer and an epitaxial multilayer that extends on the wafer along a direction from a front surface of the wafer up to an upper surface. To form an active area, a conduction region of conductive material is formed on the epitaxial multilayer. To form a contact region for biasing the first conduction region: a front trench is formed in the work body starting from the upper surface towards the back surface of the wafer, up to a contact surface; a conductive region is formed inside the front trench, on the contact surface, and in electrical contact with the first conduction region; a back trench is formed in the work body starting from the back surface towards the upper surface up to the contact surface; and a back metallization layer is formed on the back surface of the wafer and inside the back trench, on the contact surface.

Abstract: A foldable electronic device includes a first lid and a second lid rotatably coupled together by a hinge. A first inertial measurement unit (IMU) is implemented in the first lid and generates first sensor data. A second IMU is implemented in the second lid and generates second sensor data. A sensor processing unit detects the rotation angle between the first and second lids and generates rotated second sensor data by adjusting the second sensor data based on the rotation angle. The sensor processing unit generates combined sensor data by combining the first sensor data with the rotated second sensor data. The combined sensor data is more accurate than either the first sensor data or the second sensor data.

Abstract: A voltage conversion system provides gain and offset trimming for generating a controlled output voltage. The system includes a digital-to-analog converter (DAC) that generates a reference voltage based on an input code, and a voltage converter that converts an input voltage to an output voltage based on the reference voltage. A first adjustable reference circuit provides a first reference signal to the DAC and a second adjustable reference circuit provides a second reference signal to the DAC. Control circuitry adjusts the first adjustable reference circuit to perform gain trimming of the output voltage and adjusts the second adjustable reference circuit to perform offset trimming of the output voltage. A calibration procedure includes adjusting for both gain and offset, with a two-step approach for positive offset conditions—first incrementing the input code to create a negative offset, then performing offset trimming.

Abstract: A device includes a plurality of hardware accelerator islands. The accelerator islands have a plurality of processing elements, a plurality of streaming engines, and a stream switch coupled to the plurality of processing elements and to the plurality of streaming engines. The stream switch streams data between the plurality of processing elements of the accelerator island, and between the plurality of streaming engines of the accelerator island and the plurality of processing elements of the accelerator island. Unidirectional stream switch connections (SSCONNs) are coupled between pairs of stream switches of the plurality of accelerator islands. The stream switches of the plurality of hardware accelerator islands and the SSCONNs form a run-time reconfigurable interconnection mesh between the plurality of processing elements of the plurality of hardware accelerator islands.

Abstract: An electronic device includes a semiconductor body of silicon carbide, and a body region at a first surface of the semiconductor body. A source region is disposed in the body region. A drain region is disposed at a second surface of the semiconductor body. A doped region extends seamlessly at the entire first surface of the semiconductor body and includes one or more first sub-regions having a first doping concentration and one or more second sub-regions having a second doping concentration lower than the first doping concentration. Thus, the device has zones alternated to each other having different conduction threshold voltage and different saturation current.

Abstract: A control module is used to control a switching buck-boost converter that includes an inductor, a capacitor, a first top switch and a second top switch, a first bottom switch and a second bottom switch and a diode coupled to the second top switch. The control module controls the switching buck-boost converter so as to alternate: first time periods, in which the second top switch is open and cycles of charge and discharge of the inductor are carried out, during which the inductor is traversed by a current that also passes through the diode and charges the capacitor; and second time periods, in which the first and second top switches are open and the first and second bottom switches are closed so that the current in the inductor recirculates, and the capacitor is discharged by a current that flows in the load.

Abstract: According to an embodiment, a method for determining an orientation of an object in a field-of-view of a time-of-flight sensor is proposed. The method includes receiving a sensor readout from the time-of-flight sensor; feeding the sensor readout as an input to a neural network, the neural network trained on a set of data with a binary output that classifies the input as being valid or invalid based on the orientation of the object with respect to the time-of-flight sensor; rotating the sensor readout for a set number of rotations and feeding each rotation as an input to the neural network to determine a valid orientation of the object; and rotating an image on a display interface based on the rotation corresponding to the valid orientation of the object as determined by the neural network.

Abstract: In accordance with an embodiment, a circuit is configured to vary an intensity of a drive current of a resistive heater element based on the digital control signal. The circuit includes and output circuit configured to control a respective slew rate and an electric energy dissipated in the resistive heater element independently of a resistance value of the resistive heater element.

Abstract: The present disclosure relates to a pixel comprising: a photodiode comprising a portion of a substrate of a semiconductor material, extending vertically from a first face of the substrate to a second face of the substrate configured to receive light; a layer of a first material covering each of the lateral surfaces of the portion; a layer of a second material covering the portion on the side of the first face, first and second material having refractive indexes lower than that of the semiconductor material; and a diffractive structure disposed on a face of the photodiode on the side of the second face.

Abstract: A method is provided for monitoring an execution of a selected program code portion stored in a memory address range between a start address and an end address. The method includes starting a timing when a program counter points to the start address of the selected program code portion. Current values of the program counter are compared with a set of target addresses specific to the selected program code portion including the end address of the selected program code portion. The timing is stopped when the program counter points to the end address of the selected program code portion. An error signal is generated in response to the timing duration being outside a nominal duration range specific to the selected program code portion.

Abstract: A manufacturing process for microelectromechanical devices includes: on a first wafer forming a structural layer and a stop layer; defining a stop pad from the stop layer; forming a first microelectromechanical structure and a second microelectromechanical structure in the structural layer; forming a contact element protruding from a second wafer; sealing, at a first pressure, the first microelectromechanical structure in a first chamber and the second microelectromechanical structure and the stop pad in a second chamber; fluidically coupling the second chamber to an external environment; and sealing the second chamber at a second pressure. Sealing at the first pressure comprises bonding the second wafer to the first wafer so that the contact element rests on the stop pad. Fluidically coupling comprises defining fluidic passages at an interface between the contact element and the stop pad and opening an access hole through the second wafer in communication with the fluidic passages.

Abstract: A process for manufacturing a vertical conduction MOSFET device including a body of silicon carbide having a first conductivity type and a face. A metallization region extends on the face of the body. A body region of a second conductivity type extends in the body, from the face of the body, along a first direction parallel to the face and along a second direction transverse to the face. A source region of the first conductivity type extends towards the inside of the body region, from the face of the body, and has a first portion and a second portion. The first portion has a first doping level and extends in direct electrical contact with the metallization region. The second portion has a second doping level and extends in direct electrical contact with the first portion of the source region. The second doping level is lower than the first doping level.

Abstract: A process for manufacturing microelectromechanical devices includes forming a dielectric layer and a structural layer on a substrate of a first semiconductor wafer and forming a first and a second microelectromechanical device in the structural layer. The first and second microelectromechanical devices are sealed respectively in a first chamber and in a second chamber at a first pressure. The first chamber is fluidically coupled to an external environment through the substrate and sealed at a second pressure different from the first pressure. To fluidically couple the first chamber to the outside, there are formed a stop layer between the dielectric layer and the structural layer and a cavity fluidically coupled to the first chamber in the dielectric layer. A channel is formed by etching the substrate in a position corresponding to the cavity and the stop layer, and the etching of the substrate is ended against the stop layer.