Patents Assigned to Staktek Corporation
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Patent number: 5592364Abstract: The present invention includes a high density integrated circuit module which includes a plurality of stacked, individual integrated circuit devices wherein serpentine electrical interconnect rails connect electrical leads extending from the individual integrated circuit devices within the module.Type: GrantFiled: January 24, 1995Date of Patent: January 7, 1997Assignee: Staktek CorporationInventor: Jerry M. Roane
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Patent number: 5588205Abstract: The present invention includes a high density integrated circuit module which includes a plurality of stacked, individual integrated circuit devices wherein serpentine electrical interconnect rails connect electrical leads extending from the individual integrated circuit devices within the module.Type: GrantFiled: September 5, 1995Date of Patent: December 31, 1996Assignee: Staktek CorporationInventor: Jerry M. Roane
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Patent number: 5585668Abstract: This invention is for an integrated circuit package which includes two integrated circuit die connected to a common substantially planar lead frame, wherein bond pads on each die face the common lead frame.Type: GrantFiled: February 15, 1996Date of Patent: December 17, 1996Assignee: Staktek CorporationInventor: Carmen D. Burns
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Patent number: 5586009Abstract: The present invention is a rail-less bus system for a high density integrated circuit package, or module, made up of a plurality of vertically stacked high density integrated circuit devices. Each device has leads extending therefrom with bifurcated or trifurcated distal lead ends which electrically connect with lead ends of adjacent integrated circuit devices. The bus system provides a path for communication from the module to external electronic devices and internal communication between the individual integrated circuit devices in the module.Type: GrantFiled: April 9, 1996Date of Patent: December 17, 1996Assignee: Staktek CorporationInventor: Carmen D. Burns
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Patent number: 5581121Abstract: The present invention provides a method for fabricating modified integrated circuit packages that are ultra-thin and resist warping. The integrated circuit packages are made thinner by removing some of the casing material uniformly from the upper and lower major surfaces of the integrated circuit package. To prevent the resulting ultra-thin integrated circuit package from warping, a thin layer of material with a coefficient of thermal expansion less than that of silicon is mounted to the upper major surface of the package after some of the casing material has been removed uniformly from the upper major surface. Also, a thin layer of material with a coefficient of thermal expansion greater than that of silicon may be mounted to the lower major surface of the package after some of the casing material has been removed uniformly from the lower major surface. The result is an ultra-thin integrated circuit package that is thermally and mechanically balanced to prevent warping.Type: GrantFiled: July 27, 1994Date of Patent: December 3, 1996Assignee: Staktek CorporationInventors: Carmen D. Burns, James W. Cady, Jerry M. Roane, Phillip R. Troetschel
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Patent number: 5572065Abstract: A method and apparatus for achieving a hermetically sealed ceramic integrated circuit package having good thermal conductivity for efficiently transferring heat from an integrated circuit chip die contained therein. Use of an ultra-thin integrated circuit chip die, thin ceramic housing layers and external lead frame allow an ultra-thin overall package that may be used singularly or further densely packaged into a three dimensional multi-package array and still meet the critical performance and reliability requirements for both military and aerospace applications.Type: GrantFiled: October 24, 1994Date of Patent: November 5, 1996Assignee: Staktek CorporationInventor: Carmen D. Burns
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Patent number: 5566051Abstract: An ultra-thin level-one integrated circuit package with improved moisture penetration characteristics manufactured using a transfer molded casing with metallic lamination layers is provided. Additionally, a method and apparatus for providing a multiple-element modular package including a plurality of such level-one packages in horizontal or vertical stack configuration is provided.Type: GrantFiled: August 30, 1994Date of Patent: October 15, 1996Assignee: Staktek CorporationInventor: Carmen D. Burns
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Patent number: 5561591Abstract: An electrically and thermally conductive rail assembly with impedance control for interconnecting individual level-one integrated circuit packages within a three-dimensional high density integrated circuit package, and methods of manufacturing same.Type: GrantFiled: August 12, 1994Date of Patent: October 1, 1996Assignee: Staktek CorporationInventor: Carmen D. Burns
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Patent number: 5552963Abstract: The present invention is a rail-less bus system for a high density integrated circuit package, or module, made up of a plurality of vertically stacked high density integrated circuit devices. Each device has leads extending therefrom with bifurcated or trifurcated distal lead ends which electrically connect with lead ends of adjacent integrated circuit devices. The bus system provides a path for communication from the module to external electronic devices and internal communication between the individual integrated circuit devices in the module.Type: GrantFiled: July 24, 1995Date of Patent: September 3, 1996Assignee: Staktek CorporationInventor: Carmen D. Burns
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Patent number: 5550711Abstract: Thin and durable level-one and level-two integrated circuit packages are provided. A thin and durable level-one package is achieved in one method involving a molding technique of evenly applying molding compound to an integrated circuit die element. The casing surrounding a die element may be reduced or eliminated in part to thin the level-one package provided any necessary steps are taken to ensure the integrity of the package. Moisture-barriers, as an example, may be provided to the upper and/or lower surfaces of the thin level-one package. Additionally, a thin level-one package may also be constructed with one or more metal layers to prevent warpage. These level-one packages may be aligned in a stacked configuration to form a thin and durable horizontal level-two package. Various thermal conductors may be thermally coupled to the level-two package to help dissipate heat.Type: GrantFiled: May 8, 1995Date of Patent: August 27, 1996Assignee: Staktek CorporationInventors: Carmen D. Burns, Jerry Roane, James W. Cady
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Patent number: 5543664Abstract: An ultra-thin level-one integrated circuit package with improved moisture penetration characteristics manufactured using a transfer molded casing with metallic lamination layers is provided. Additionally, a method and apparatus for providing a multiple-element modular package including a plurality of such level-one packages in horizontal or vertical stack configuration is provided.Type: GrantFiled: January 20, 1995Date of Patent: August 6, 1996Assignee: Staktek CorporationInventor: Carmen D. Burns
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Patent number: 5528075Abstract: A method and apparatus for achieving lead-on-chip integrated circuit packages by transferring at least one extremely thin adhesive from a carrier onto the face of integrated circuit chips, laminating a lead frame to the last adhesive layer, curing the adhesive to act as an insulator, bonding to the integrated circuit chip connection pads and encapsulating the chip and lead frame. A polypropylene carrier having adhesive patches pre-shaped and oriented in relation to the integrated circuit chips is brought into contact with the heated chips by either vacuum or pressure action wherein the adhesive is transferred from the polypropylene carrier to the faces of the chips. Thermally conductive and electrically insulating filling may be used with the adhesive to improve heat conduction from the IC. Compliant adhesive reduces thermally induced stresses between the lead frame and IC chip.Type: GrantFiled: January 20, 1995Date of Patent: June 18, 1996Assignee: Staktek CorporationInventor: Carmen D. Burns
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Patent number: 5498906Abstract: The present invention provides capacitive and/or power supply decoupling for an integrated circuit package by utilizing an externally mounted bypass capacitor between power and ground. The bypass capacitor is mounted on internal leads projecting into a cove area formed at one or both ends of an integrated circuit package whereby one such internal lead is connected to the external power lead and the other such internal lead is connected to the external ground lead. A flexible, high-temperature adhesive material is used to secure the capacitor to the internal leads in the cove of the IC package so that when the package is later subject to soldering temperature thereby softening the solder connections between internal leads and the capacitor, the capacitor will not be electrically or physically disconnected from the internal leads. The adhesive secures the capacitor in place until the high temperatures dissipate and the solder joints between capacitor and the internal leads harden.Type: GrantFiled: November 17, 1993Date of Patent: March 12, 1996Assignee: Staktek CorporationInventors: Jerry M. Roane, Carmen D. Burns
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Patent number: 5499160Abstract: A high density integrated circuit module which includes a plurality of stacked integrated circuit packages, wherein each package includes a casing, an integrated circuit die disposed within the casing and a plurality of electrical interconnect leads extending from the die through the casing; also including a plurality of electrically and thermally conductive vertical rails.Type: GrantFiled: January 30, 1995Date of Patent: March 12, 1996Assignee: Staktek CorporationInventor: Carmen D. Burns
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Patent number: 5493476Abstract: The present invention is a rail-less bus system for a high density integrated circuit package, or module, made up of a plurality of vertically stacked high density integrated circuit devices. Each device has leads extending therefrom with bifurcated or trifurcated distal lead ends which electrically connect with lead ends of adjacent integrated circuit devices. The bus system provides a path for communication from the module to external electronic devices and internal communication between the individual integrated circuit devices in the module.Type: GrantFiled: May 22, 1995Date of Patent: February 20, 1996Assignee: Staktek CorporationInventor: Carmen D. Burns
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Patent number: 5484959Abstract: The present invention provides a method and apparatus for fabricating thermally and electrically improved electronic integrated circuits by laminating one or more lead frames to a standard integrated circuit package such as, for example, thin small outline package (TSOP). The lead frame laminated to the package enhances thermal conduction of heat from the integrated circuit package. A heat spreader may also be utilized to improve heat transfer and can be further used as a ground plane to improve signal quality by reducing electrical circuit noise. Achieving improved thermal transfer characteristics from an integrated circuit package results in better dissipation of heat from the integrated circuit package and results in more reliable operation thereby. Using standard commercially available integrated circuit packages such as TSOP allows economical and rapid fabrication of thermally and electrically superior electronic circuits for applications that demand high reliability and performance.Type: GrantFiled: December 11, 1992Date of Patent: January 16, 1996Assignee: Staktek CorporationInventor: Carmen D. Burns
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Patent number: 5479318Abstract: The present invention is a rail-less bus system for a high density integrated circuit package, or module, made up of a plurality of vertically stacked high density integrated circuit devices. Each device has leads extending therefrom with bifurcated or trifurcated distal lead ends which electrically connect with lead ends of adjacent integrated circuit devices. The bus system provides a path for communication from the module to external electronic devices and internal communication between the individual integrated circuit devices in the module.Type: GrantFiled: May 12, 1995Date of Patent: December 26, 1995Assignee: Staktek CorporationInventor: Carmen D. Burns
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Patent number: 5455740Abstract: The present invention is a rail-less bus system for a high density integrated circuit package, or module, made up of a plurality of vertically stacked high density integrated circuit devices. Each device has leads extending therefrom with bifurcated or trifurcated distal lead ends which electrically connect with lead ends of adjacent integrated circuit devices. The bus system provides a path for communication from the module to external electronic devices and internal communication between the individual integrated circuit devices in the module.Type: GrantFiled: March 7, 1994Date of Patent: October 3, 1995Assignee: Staktek CorporationInventor: Carmen D. Burns
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Patent number: 5448450Abstract: A lead-on-chip integrated circuit package comprising at least one extremely thin adhesive layer transferred from a carrier onto the face of integrated circuit chips, and a lead frame laminated to the last adhesive layer, with cured adhesive acting as an insulator, integrated circuit chip connection pads bonded to and encapsulating the chip and lead frame. Thermally conductive and electrically insulating filling may be included with the adhesive to improve heat conduction from the IC. Compliant adhesive reduces thermally induced stresses between the lead frame and IC chip. Both the improved thermal performance and reduced moisture absorption of the encapsulated package improves the reliability of the integrated circuit package.Type: GrantFiled: October 28, 1991Date of Patent: September 5, 1995Assignee: Staktek CorporationInventor: Carmen D. Burns
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Patent number: 5446620Abstract: Thin and durable level-one and level-two integrated circuit packages are provided. Moisture-barriers may be provided to upper and/or lower surfaces of the thin level-one package. Additionally, a thin level-one package may be constructed with one or more metal layers to prevent warpage. These level-one packages are aligned in a stacked configuration to form a thin and durable horizontal level-two package. Various thermal conductors are thermally coupled to the level-two package to help dissipate heat.Type: GrantFiled: October 8, 1993Date of Patent: August 29, 1995Assignee: Staktek CorporationInventors: Carmen D. Burns, Jerry Roane, James W. Cady