Abstract: Thin and durable level-one and level-two integrated circuit packages are provided. A thin and durable level-one package is achieved in one method involving a molding technique of evenly applying molding compound to an integrated circuit die element. The casing surrounding a die element may be reduced or eliminated in part to thin the level-one package provided any necessary steps are taken to ensure the integrity of the package. Moisture-barriers, as an example, may be provided to the upper and/or lower surfaces of the thin level-one package. Additionally, a thin level-one package may also be constructed with one or more metal layers to prevent warpage. These level-one packages may be aligned in a stacked configuration to form a thin and durable horizontal level-two package. Various thermal conductors may be thermally coupled to the level-two package to help dissipate heat.

Abstract: Thin and durable level-one and level-two integrated circuit packages are provided. A thin and durable level-one package is achieved in one method involving a molding technique of evenly applying molding compound to an integrated circuit die element. The casing surrounding a die element may be reduced or eliminated in part to thin the level-one package provided any necessary steps are taken to ensure the integrity of the package. Moisture-barriers, as an example, may be provided to the upper and/or lower surfaces of the thin level-one package. Additionally, a thin level-one package may also be constructed with one or more metal layers to prevent warpage. These level-one packages may be aligned in a stacked configuration to form a thin and durable horizontal level-two package. Various thermal conductors may be thermally coupled to the level-two package to help dissipate heat.

Abstract: The present invention is a rail-less bus system for a high density integrated circuit package, or module, made up of a plurality of vertically stacked high density integrated circuit devices. Each device has leads extending therefrom with bifurcated or trifurcated distal lead ends which electrically connect with lead ends of adjacent integrated circuit devices. The bus system provides a path for communication from the module to external electronic devices and internal communication between the individual integrated circuit devices in the module.

Abstract: A high density integrated circuit module having complex electrical interconnection is described, which includes a plurality of stacked level-one integrated circuit devices, wherein each level-one device includes an integrated circuit die and a plurality of electrical leads extending from the die; and a plurality of non-linear rails adapted to electrically and thermally interconnect selected leads of selected stacked level-one devices within the module, wherein at least some of the plurality of non-linear rail include a lead interconnect portion which is adapted to at most partially surround and receive a selected lead from one of the stacked level-one devices. Other embodiments include TSOP modules having leads reduced in width to allow additional selected non-linear rails to interconnect with select leads in the module. Strain relief for the rail/circuit board substrate connection in harsh environment applications is also provided.

Abstract: An integrated circuit package for improved warp resistance and heat dissipation is described. The LOC package includes: an integrated circuit die having an upper, active face, and a multi-layered, substantially planar lead frame mounted to the active face of the die, where the lead frame is preferably comprised of layers configured as Cu/INVAR/Cu or Cu/Alloy 42/Cu. The choice of the middle layer of the lead frame is selected to minimize the warping forces on the package such that the coefficient of thermal expansion of the composite lead frame approximates that of silicon. The copper layers of the lead frame provide improved heat dissipation.

Abstract: A method and apparatus for achieving a three-dimensional high density warp-resistant integrated circuit module is provided. Selected individual integrated circuit packages which comprise the module are mounted with a thin stiffener, or a thin layer of material having a coefficient of thermal expansion (CTE) less than or equal to that of silicon, and/or are lapped to reduce the package profile, and/or are mounted with a thin layer of material having a CTE greater than that of silicon, and preferably approximately equal to that of the casing material.

Abstract: The present invention provides a method for fabricating modified integrated circuit packages that are ultra-thin and resist warping. The integrated circuit packages are made thinner by removing some of the casing material uniformly from the upper and lower major surfaces of the integrated circuit package. To prevent the resulting ultra-thin integrated circuit package from warping, a thin layer of material with a coefficient of thermal expansion less than that of silicon is mounted to the upper major surface of the package after some of the casing material has been removed uniformly from the upper major surface. Also, a thin layer of material with a coefficient of thermal expansion greater than that of silicon may be mounted to the lower major surface of the package after some of the casing material has been removed uniformly from the lower major surface. The result is an ultra-thin integrated circuit package that is thermally and mechanically balanced to prevent warping.

Abstract: An ultra high-density integrated circuit module which includes a plurality of individual high-density integrated circuit packages. A plurality of the ultra high-density integrated circuit memory modules may be combined to form an ultra high-density memory bank for use in computers, or other applications requiring high-density on-board memory. The high-density integrated circuit packages which form the modules each have an internal lead frame and optional internal member which overlie an integrated circuit die. A thin, warp-resistant metal layer and an external heat conductor element are mounted to the exterior of the package. Heat is dissipated from the package while structural forces are selectively balanced.

Abstract: An ultra high-density integrated circuit module which includes a plurality of individual high-density integrated circuit packages. A plurality of the ultra high-density integrated circuit memory modules may be combined to form an ultra high-density memory bank for use in computers, or other applications requiring high-density on-board memory. The high-density integrated circuit packages which form the modules each have an internal lead frame and optional internal member which overlie an integrated circuit die. A thin, warp-resistant metal layer and an external heat conductor element are mounted to the exterior of the package. Heat is dissipated from the package while structural forces are selectively balanced.

Abstract: A hermetically sealed ceramic integrated circuit package and method for achieving same, the package including an internal lead frame attached to an integrated circuit die in a lead-on-chip configuration, an external lead frame attached to the package exterior in a lead-on-package configuration and a high temperature adhesive layer which attaches the internal lead frame to the integrated circuit die.

Abstract: A method and apparatus for achieving a three-dimensional high density warp-resistant integrated circuit module is provided. Selected individual integrated circuit packages which comprise the module are mounted with a thin stiffener, or a thin layer of material having a coefficient of thermal expansion (CTE) less than or equal to that of silicon, and/or are lapped to reduce the package profile, and/or are mounted with a thin layer of material having a CTE greater than that of silicon, and preferably approximately equal to that of the casing material.

Abstract: A hermetically sealed ceramic integrated circuit package and method for achieving same, the package including an internal lead frame attached to an integrated circuit die in a lead-on-chip configuration, an external lead frame attached to the package exterior in a lead-on-package configuration and a high temperature adhesive layer which attaches the internal lead frame to the integrated circuit die.

Abstract: A high density integrated circuit module having complex electrical interconnection is described, which includes a plurality of stacked level-one integrated circuit devices, wherein each level-one device includes an integrated circuit die and a plurality of electrical leads extending from the die; and a plurality of non-linear rails adapted to electrically and thermally interconnect selected leads of selected stacked level-one devices within the module, wherein at least some of the plurality of non-linear rail include a lead interconnect portion which is adapted to at most partially surround and receive a selected lead from one of the stacked level-one devices. Other embodiments include TSOP modules having leads reduced in width to allow additional selected non-linear rails to interconnect with select leads in the module. Strain relief for the rail/circuit board substrate connection in harsh environment applications is also provided.

Abstract: A method for achieving a hermetically sealed ceramic integrated circuit package having good thermal conductivity for efficiently transferring heat from an integrated circuit chip die contained therein. Use of an ultra-thin integrated circuit chip die, thin ceramic housing layers and external lead frame allow an ultra-thin overall package that may be used singularly or further densely packaged into a three dimensional multi-package array and still meet the critical performance and reliability requirements for both military and aerospace applications.

Abstract: A lead-on-chip integrated circuit assembly comprising at least one extremely thin adhesive layer transferred from a carrier onto the face of an integrated circuit chip, and a lead frame laminated to the last adhesive layer, with cured adhesive acting as an insulator, wherein said lead frame is aligned and connected to integrated circuit chip connection pads. This lead-on-chip integrated circuit assembly may be encapsulated. Thermally conductive and electrically insulating filling may be included with the adhesive to improve heat conduction from the integrated circuit ("IC"). Compliant adhesive reduces thermally induced stresses between the lead frame and IC chip. Both the improved thermal performance and reduced moisture absorption of the encapsulated assembly improves the reliability of the integrated circuit package.

Abstract: An ultra high-density integrated circuit module which includes a plurality of individual high-density integrated circuit packages. A plurality of the ultra high-density integrated circuit memory modules may be combined to form an ultra high-density memory bank for use in computers, or other applications requiring high-density on-board memory. The high-density integrated circuit packages which form the modules each have an internal lead frame and optional internal member which overlie an integrated circuit die. A thin, warp-resistant metal layer and an external heat conductor element are mounted to the exterior of the package. Heat is dissipated from the package while structural forces are selectively balanced.

Abstract: The present invention provides a method and apparatus for fabricating thermally and electrically improved electronic integrated circuits by laminating one or more lead frames to a standard integrated circuit package such as, for example, a thin small outline package (TSOP). The lead frame laminated to the package enhances thermal conduction of heat from the integrated circuit package. A heat spreader may also be utilized to improve heat transfer and can be further used as a ground plane to improve signal quality by reducing electrical circuit noise. Achieving improved thermal transfer characteristics from an integrated circuit package results in better dissipation of heat from the integrated circuit package and results in more reliable operation thereby. Using standard commercially available integrated circuit packages such as TSOP allows economical and rapid fabrication of thermally and electrically superior electronic circuits for applications that demand high reliability and performance.

Abstract: This invention is for an integrated circuit package which includes two integrated circuit die connected to a common substantially planar lead frame, wherein bond pads on each die face the common lead frame.

Abstract: The present invention is a rail-less bus system for a high density integrated circuit package, or module, made up of a plurality of vertically stacked high density integrated circuit devices. Each device has leads extending therefrom with bifurcated or trifurcated distal lead ends which electrically connect with lead ends of adjacent integrated circuit devices. The bus system provides a path for communication from the module to external electronic devices and internal communication between the individual integrated circuit devices in the module.

Abstract: The memory addressing system of the present invention incorporates industry standard features for compatibility and adds the capability of using high-density module memory boards exclusively or in combination with current or next generation standard memory modules without increasing system power requirements. The system provides a plurality of standardized memory module circuit board sockets that are electrically connected so as to provide address decoded RAS signals in addition to the standard row and column addressing signals.