Abstract: An integrated electronic circuit including: a dielectric body delimited by a front surface; A top conductive region of an integrated electronic circuit extend within a dielectric body having a front surface. A passivation structure including a bottom portion and a top portion laterally delimits an opening. The bottom portion extends on the front surface, and the top portion extends on the bottom portion. A field plate includes an internal portion and an external portion. The internal portion is located within the opening and extends on the top portion of the passivation structure. The external portion extends laterally with respect to the top portion of the passivation structure and contacts at a bottom one of: the dielectric body or the bottom portion of the passivation structure. The opening and the external portion are arranged on opposite sides of the top portion of the passivation structure.
Abstract: A system on chip includes a monitoring circuit that detects an anomalous behavior of the system on chip. The monitoring circuit compares a behavior of the system on chip to at least one reference parameter representing the anomalous behavior of the system. Using this comparison, the anomalous behavior of the system on chip is detected. An interrupt is the issued in response to the detected anomalous behavior of the system on chip.
Abstract: A MEMS actuator includes a mobile mass suspended over a substrate in a first direction and extending in a plane that defines a second direction and a third direction perpendicular thereto. Elastic elements arranged between the substrate and the mobile mass have a first compliance in a direction parallel to the first direction that is lower than a second compliance in a direction parallel to the second direction. Piezoelectric actuation structures have a portion fixed with respect to the substrate and a portion that deforms in the first direction in response to an actuation voltage. Movement-transformation structures coupled to the piezoelectric actuation structures include an elastic movement-conversion structure arranged between the piezoelectric actuation structures and the mobile mass. The elastic movement-conversion structure is compliant in a plane formed by the first and second directions and has first and second principal axes of inertia transverse to the first and second directions.
Type:
Application
Filed:
May 24, 2022
Publication date:
December 1, 2022
Applicant:
STMicroelectronics S.r.l.
Inventors:
Nicolo' BONI, Gabriele GATTERE, Manuel RIANI, Roberto CARMINATI
Abstract: An embodiment apparatus comprises a switching-type output power stage, a modulator circuit configured for carrying out a pulse-width modulation and converting an electrical input signal into an input signal pulsed between two electrical levels, having a mean value proportional to the amplitude of the input signal, and a circuit arrangement for controlling saturation of an output signal supplied by the switching-type output power stage. The circuit arrangement comprises a pulse-remodulator circuit, between the output of the modulator circuit and the input of the switching-type output power stage, that is configured for supplying, as a driving signal to the switching-type output power stage, a respective modulated signal pulsed between two electrical levels, measuring a pulse width as pulse time interval elapsing between two consecutive pulsed-signal edges of the pulsed input signal, and, if the measurement indicates that the latter is below a given minimum value, remodulating the pulsed input signal.
Abstract: A lead frame for an integrated electronic device includes a die pad made of a first metallic material. A top coating layer formed by a second metallic material is arranged on a top surface of the die pad. The second metallic material has an oxidation rate lower than the first metallic material. The top coating layer leaves exposed a number of corner portions of the top surface of the die pad. A subsequent heating operation, for example occurring in connection with wirebonding, causes an oxidized layer to form on the corner portions of the top surface of the die pad at a position in contact with the top coating layer.
Abstract: An ESD protection circuit includes a terminal connected to the cathode of a first diode and to the anode of a second diode, where the cathode of the second diode is not made of epitaxial silicon.
Abstract: A microelectromechanical mirror device has, in a die of semiconductor material: a fixed structure defining a cavity; a tiltable structure carrying a reflecting region elastically suspended above the cavity; at least a first pair of driving arms coupled to the tiltable structure and carrying respective piezoelectric material regions which may be biased to cause a rotation thereof around at least one rotation axis; elastic suspension elements coupling the tiltable structure elastically to the fixed structure and which are stiff with respect to movements out of the horizontal plane and yielding with respect to torsion; and a piezoresistive sensor configured to provide a detection signal indicative of the rotation of the tiltable structure. At least one test structure is integrated in the die to provide a calibration signal indicative of a sensitivity variation of the piezoresistive sensor in order to calibrate the detection signal.
Abstract: Current signals indicative of sensed physical quantities are collected from sensing transistors in an array of sensing transistors. The sensing transistors have respective control nodes and current channel paths therethrough between respective first nodes and a second node common to the sensing transistors. A bias voltage level is applied to the respective first nodes of the sensing transistors in the array and one sensing transistor in the array of sensing transistors is selected. The selected sensing transistor is decoupled from the bias voltage level, while the remaining sensing transistors in the array of sensing transistors maintain coupling to the bias voltage level. The respective first node of the selected sensing transistor in the array of sensing transistors is coupled to an output node, and an output current signal is collected from the output node.
Abstract: A system for detecting a presence in an environment to be monitored includes an electrostatic charge variation sensor, a vibration sensor, and an environmental pressure sensor. A processing unit is configured to acquire, from the electrostatic charge variation sensor, an electrostatic charge variation signal, and detect in the electrostatic charge variation signal, first signal characteristics indicative of the presence of a subject in the environment to be monitored. The processing unit further validates the detection of presence of the subject using the vibration and pressure signals provided by the other sensors.
Abstract: A method of performing an electro-thermo simulation includes defining a non-linear heat diffusion problem for at least a portion of a semiconductor device to be modeled, performing a finite volume discretization of the non-linear heat diffusion problem, reformulating a non-linear term of the discretized non-linear heat diffusion problem to decrease dimensions thereof, performing a hyper reduction of the reformulated non-linear term, and recovering the non-linear heat diffusion problem for the portion of the semiconductor device, and manufacturing the modeled semiconductor device.
Type:
Application
Filed:
April 29, 2021
Publication date:
November 17, 2022
Applicant:
STMicroelectronics S.r.l.
Inventors:
Nicolo FOLLONI, Mattia MONETTI, Diego CARRERA, Beatrice ROSSI, Giancarlo ZINCO, Alberto BALZAROTTI, Pasqualina FRAGNETO
Abstract: A method can be used to test an electronic circuit. The method includes applying a test stimulus signal to the input node, collecting a sequence of N-bit digital test data at the output port. The N-bit digital test data is determined by the test stimulus signal applied to the input node. The method also includes applying N-bit to R-bit lossless compression to the N-bit digital test data to obtain R-bit compressed test data (R is less than N) and making the R-bit compressed test data available in parallel format over R output pins of the circuit.
Abstract: The present disclosure relates to a method and device for performing an elliptic curve cryptography computation comprising: twisting, by a first device based on a first index of quadratic or higher order twist (d), a first point (P?KB) on a first elliptic curve over a further elliptic curve twisted with respect to the first elliptic curve to generate a twisted key (PKB); transmitting the twisted key (PKB) to a further device; receiving, from the further device, a return value (ShS) generated based on the twisted key (PKB); and twisting, by the first device based on the first index of quadratic or higher order twist (d), the return value (ShS) over the first elliptic curve to generate a result (ShS?) of the ECC computation.
Abstract: A control circuit for a multiphase buck converter includes a regulator circuit and a plurality of phase control circuits. The regulator circuit generates a regulation signal based on a feedback signal and a reference signal, and each phase control circuit receives a current sense signal and generates a respective PWM signal based on the respective current sense signal and the regulation signal. The control circuit includes a first selector circuit and a second selector circuit configured to receive a selection signal and selectively connect each phase control circuit of a subset of the phase control circuits to a PWM signal for driving a respective stage of the multiphase buck converter, and to a current sense signal provided by the respective stage of the multiphase buck converter. A selection control circuit generates the selection signal in order to connect the phase control circuits to different stages of the multiphase buck converter.
Abstract: An electronic power device includes a substrate of silicon carbide (SiC) having a front surface and a rear surface which lie in a horizontal plane and are opposite to one another along a vertical axis. The substrate includes an active area, provided in which are a number of doped regions, and an edge area, which is not active, distinct from and surrounding the active area. A dielectric region is arranged above the front surface, in at least the edge area. A passivation layer is arranged above the front surface of the substrate, and is in contact with the dielectric region in the edge area. The passivation layer includes at least one anchorage region that extends through the thickness of the dielectric region at the edge area, such as to define a mechanical anchorage for the passivation layer.
Type:
Grant
Filed:
September 30, 2020
Date of Patent:
November 8, 2022
Assignee:
STMicroelectronics S.r.l.
Inventors:
Simone Rascuna′, Claudio Chibbaro, Alfio Guarnera, Mario Giuseppe Saggio, Francesco Lizio
Abstract: The present disclosure relates to a method for controlling a device comprising an oscillation circuit, configured to provide a clock signal to a radio frequency circuit, and an antenna, in which the enabling of the passage of the signal from the circuit to the antenna is delayed with respect to an instant from which a power amplifier of the circuit is enabled.
Type:
Grant
Filed:
February 20, 2021
Date of Patent:
November 8, 2022
Assignees:
STMicroelectronics (Alps) SAS, STMicroelectronics S.r.l., STMicroelectronics (Grenoble 2) SAS
Inventors:
Benoit Marchand, Hamilton Emmanuel Querino De Carvalho, Daniele Mangano, Santo Leotta
Abstract: A voltage supply circuit and a method for controlling a voltage supply circuit are provided. The voltage supply circuit includes a positive charge pump stage that generates a positive voltage and a negative charge pump stage that generates a negative voltage. The voltage supply circuit also includes a control stage that compares a voltage representative of the negative voltage with a reference voltage and causes a slope of the positive voltage to decrease when the voltage representative of the negative voltage exceeds the reference voltage.
Type:
Application
Filed:
July 15, 2022
Publication date:
November 3, 2022
Applicants:
STMicroelectronics International N.V., STMicroelectronics S.r.l.
Inventors:
Vikas Rana, Marco Pasotti, Fabio De Santis
Abstract: A process for manufacturing a microelectromechanical mirror device includes, in a semiconductor wafer, defining a support frame, a plate connected to the support frame so as to be orientable around at least one rotation axis, and cantilever structures extending from the support frame and coupled to the plate so that bending of the cantilever structures causes rotations of the plate around the at least one rotation axis. The process further includes forming piezoelectric actuators on the cantilever structures, forming pads on the support frame, and forming spacer structures protruding from the support frame more than both the pads and the stacks of layers forming the piezoelectric actuators.
Abstract: A substrate includes electrically-conductive tracks. A semiconductor chip is arranged on the substrate and electrically coupled to selected ones of the electrically-conductive tracks. Containment structures are provided at selected locations on the electrically-conductive tracks, where the containment structures have respective perimeter walls defining respective cavities. Each cavity is configured to accommodate a base portion of a pin holder. These pin holders are soldered to the electrically-conductive tracks within the cavities defined by the containment structures. Each containment structure may be formed by a ring of resist material configured to receive solder and maintain the pin holders in a desired alignment position.
Abstract: A substrate made of doped single-crystal silicon has an upper surface. A doped single-crystal silicon layer is formed by epitaxy on top of and in contact with the upper surface of the substrate. Either before or after forming the doped single-crystal silicon layer, and before any other thermal treatment step at a temperature in the range from 600° C. to 900° C., a denuding thermal treatment is applied to the substrate for several hours. This denuding thermal treatment is at a temperature higher than or equal to 1,000° C.
Type:
Application
Filed:
April 26, 2022
Publication date:
November 3, 2022
Applicants:
STMicroelectronics S.r.l., STMicroelectronics (Crolles 2) SAS
Inventors:
Pierpaolo MONGE ROFFARELLO, Isabella MICA, Didier DUTARTRE, Alexandra ABBADIE
Abstract: A semiconductor device, such as a QFN (Quad-Flat No-lead) package, includes an insulating encapsulation of a semiconductor chip. The insulating encapsulation is formed by a first encapsulation material which encapsulates the semiconductor chip and a second encapsulation material that is molded onto an upper surface of the first encapsulation material. The first encapsulation material includes an oblique cavity extending from the upper surface. The second encapsulation material includes an anchoring protrusion that enters into the cavity.
Type:
Application
Filed:
April 25, 2022
Publication date:
November 3, 2022
Applicant:
STMicroelectronics S.r.l.
Inventors:
Antonio BELLIZZI, Antonio CANNAVACCIUOLO