Abstract: A converter circuit includes a half-bridge power circuit with a first and a second switch between an input node and a current node and between the current node ground, respectively. An inductor is coupled between the current node and an output node. Logic control circuitry is configured to switch the first and second switches to a current recirculation state and to a current charge state. The logic circuitry is configured to switch the switches from the current recirculation state to the current charge state as a result of a voltage indicator signal from an output voltage comparator being asserted while starting an on-time counter signal having an expiration value, and from the current charge state to the current recirculation state as a result of the on-time counter signal having reached its expiration value in combination with the voltage indicator signal from the voltage comparator being de-asserted.

Abstract: A Single Input Dual Output converter includes a first switch coupling an input to a first inductor terminal, a second switch coupling a second inductor terminal to ground, a third switch coupling the second inductor terminal to a positive output, and a fourth switch coupling the first inductor terminal to a negative output. During time-shared control, the negative and positive outputs are independently served by conversion cycles. Each conversion cycle includes: a positive phase with a positive charge phase (closing only the first and second switches), followed by an additional phase (closing only the first and third switches for a given time duration), and followed by a positive discharge phase (closing only the third and fourth switches). Each conversion cycle further includes a negative phase with a negative charge phase (closing only the first and second switches) followed by a negative discharge phase (closing only the second and fourth switches).

Abstract: The present disclosure relates to a device comprising an inductive element and a first capacitive element series connected between a first node and a second node, a first MOS transistor connected between the first node and a third node configured to receive a reference potential, the second node being coupled directly or via a second MOS transistor to the third node, a second capacitive element connected between a fourth node and an interconnection node between the first capacitive element and the inductive element, a current generator configured to provide an AC current to the fourth node, and a switch connected between the fourth node and the third node.

Abstract: An embodiment provides a circuit including a transformer having a primary winding coupled to an input port configured to receive an input voltage and a secondary winding configured to provide an output voltage at an output port, controller circuitry configured to switch on and off a current through the primary winding so that energy is transferred to the secondary winding while switching and supply circuitry connected to the controller circuitry, wherein the supply circuitry is coupled to an auxiliary winding of the transformer and configured to provide a supply voltage for the controller circuitry.

Abstract: A device for monitoring the health state is made in a chip including a semiconductor die integrating an electric potential sensor and a cardiac parameter determination unit. The potential sensor is configured to detect potential variations on the body of a living being and associated with a heart rhythm and to generate a cardiac signal. The cardiac parameter determination unit is configured to receive the cardiac signal and determine cardiac parameters indicative of a health state. In particular, the cardiac parameter determination unit is configured to detect triggering events and to determine features of the cardiac signal in time windows defined by the triggering events. The die also integrates a decision unit, configured to receive the cardiac parameters and generate a health signal based on a comparison with threshold values. The cardiac parameters include heart rate and QRS-complex.

Abstract: A semiconductor device includes a pre-molded leadframe mounting substrate. The substrate includes a die pad (configured to have a semiconductor die mounted thereon) and a first electrically conductive pad and a second electrically conductive pad. A strip of insulating material is molded between the first and second electrically conductive pads to provide a mutually electrically insulation and extends in a longitudinal direction with the first electrically conductive pad and the second electrically conductive pad lying on opposite sides of the strip of insulating material. A semiconductor die is arranged on the die pad in register with the strip of insulating material. A single electrically conductive ribbon extending in register with the strip of insulating material electrically couples the semiconductor die with both the first and second electrically conductive pads to provide a common current flow path from the semiconductor die towards the first and the second electrically conductive pads.

Abstract: A road condition detection device, to be coupled to the wheel of a vehicle, is provided with: an electrostatic charge variation sensor, to provide a charge variation signal indicative of an electrostatic charge variation associated with the rotation of the wheel; and a processing unit, coupled to the electrostatic charge variation sensor to receive the charge variation signal and furthermore for receiving a rotation speed signal indicative of the rotation speed of the wheel. In particular, the processing unit jointly processes the rotation speed signal and the charge variation signal to detect a road condition of a wet road condition and a dry road condition.

Abstract: A tamper resistant device can be used for an integrated circuit card. The device includes memory storing a first security domain that includes a telecommunication profile and a second security domain that includes an application profile. A first physical interface is configured to be coupled to a baseband processor configured to operate with a mobile telecommunications network. A second physical interface configured to be coupled to an application processor. The first physical interface configured to allow the baseband processor to access the telecommunication profile and the second physical interface is configured to allow the application processor to access the application profile. The tamper resistant device is configured to enable accessibility to the application profile if corresponding commands are received at the first interface and to enable accessibility to the telecommunication profile if corresponding commands are received at the second interface.

Abstract: A method of operating electro-acoustical transducers such as PMUTs involves applying to the transducer an excitation signal over an excitation interval, acquiring at the transducer a ring-down signal indicative of the ring-down behavior of the transducer after the end of the excitation interval, and calculating, as a function of said ring-down signal, a resonance frequency of the electro-acoustical transducer. A bias voltage of the electro-acoustical transducer can be controlled as a function of the resonance frequency. An acoustical signal received can be transduced into an electrical reception signal and a damping parameter of the electro-acoustical transducer can be calculated as a function of the ring-down signal so that a cross-correlation reference signal can be synthesized as a function of the resonance frequency and the damping ratio of the electro-acoustical transducer.

Abstract: A method includes pre-charging a parasitic capacitance of a control node that is coupled to a control terminal of first and second transistors that have respective current paths that form a switched current path coupled between a load node and a storage node. Pre-charging the parasitic capacitance includes: making conductive a first auxiliary transistor that has a current path coupled between the storage node and the control node, or making conductive a second auxiliary transistor that has a current path coupled between the load node and the control node. The method further includes, after pre-charging the parasitic capacitance, making the switched current path conductive to couple the load node to the storage node.

Abstract: A control circuit includes: an output terminal configured to be coupled to a control terminal of a transistor that has a current path coupled to an inductor; a transconductance amplifier configured to produce a sense current based on a current flowing through the current path of the transistor; and a first capacitor, where the control circuit is configured to: turn on the transistor based on a clock signal, integrate the sense current with an integrating capacitor to generate a first voltage, generate a second voltage across the first capacitor based on a first current, generate a second current based on the second voltage, generate a third voltage based on the second current, turn off the transistor when the first voltage becomes higher than the third voltage; discharge the integrating capacitor when the transistor turns off; and regulate an average output current flowing through the inductor based on the first current.

Abstract: Semiconductor devices are arranged in a chain extending in a longitudinal direction have mutually facing end sides transverse the longitudinal direction and are coupled via tie bars located at the mutually facing end sides. The tie bars are provided with anchoring tips penetrating into an insulating package at mutually facing end sides of the devices. The tie bars can be deformed to extract the anchoring tips from the insulating package at the mutually facing end sides of the devices. Individual singulated devices are thus produced in response to the anchoring tips being extracted from the mutually facing end sides of the devices.

Abstract: A circuit includes a high-side transistor pair and a low-side transistor pair having a common intermediate node. The high-side transistor pair includes a first transistor having a control node and a current flowpath therethrough configured to provide a current flow line between a supply voltage node and the intermediate node, and a second transistor having a current flowpath therethrough coupled to the control node of the first transistor. The low-side transistor pair includes a third transistor having a control node and a current flowpath therethrough configured to provide a current flow line between the intermediate node and the reference voltage node, and a fourth transistor having a current flowpath therethrough coupled to the control node of the third transistor. Testing circuitry is configured to be coupled to at least one of the second transistor and the fourth transistor to apply thereto a test-mode signal.

Abstract: A circuit comprises first and second input supply nodes configured to receive a supply voltage therebetween. The circuit comprises a high-side driver circuit configured to be coupled to a high-side switch and produce a first signal between first and second high-side output nodes. The circuit comprises a low-side driver circuit configured to be coupled to a low-side switch and produce a second signal between first and second low-side output nodes. The circuit comprises a floating node configured to receive a floating voltage applied between the floating node and the second high-side output node, a bootstrap diode between the first input supply node and an intermediate node, and a current limiter circuit between the intermediate node and the floating node and configured to sense the floating voltage and counter a current flow from the intermediate node to the floating node as a result of the floating voltage reaching a threshold value.

Abstract: In various embodiments, the present disclosure provides capacitors and methods of forming capacitors. In one embodiment, a capacitor includes a substrate, a first electrode on the substrate, a second electrode, and a first dielectric layer. A portion of the first electrode is exposed in a contact region. The first dielectric layer includes a first dielectric region between the first electrode and the second electrode, and a second dielectric region between the first dielectric region and the contact region. The second dielectric region is contiguous to the first dielectric region, and a surface of the second dielectric region defines a surface path between the first electrode and the contact region. The second dielectric region has a plurality of grooves that increase a spatial extension of said surface path.

Abstract: A pre-molded leadframe includes a laminar structure having empty spaces therein and a first thickness with a die pad having opposed first and second die pad surfaces. Insulating pre-mold material is molded onto the laminar structure. The pre-mold material penetrates the empty spaces and provides a laminar pre-molded substrate having the first thickness with the first die pad surface left exposed. The die pad has a second thickness that is less than the first thickness. One or more pillar formations are provided protruding from the second die pad surface to a height equal to a difference between the first and second thicknesses. With the laminar structure clamped between surfaces of a mold, the first die pad surface and pillar formations abut against the mold surfaces. The die pad is thus effectively clamped between the clamping surfaces countering undesired flashing of the pre-mold material over the first die pad surface.

Abstract: First and second circuit branches are coupled between an input node and ground. Each circuit branch includes a series coupling first-fourth transistors in a current flow path with an output node. A first capacitor is coupled between a first capacitor node and a second capacitor node intermediate the first transistor and the second transistor in the first circuit branch. A second capacitor is coupled between a third capacitor node and a fourth capacitor node intermediate the first transistor and the second transistor in the second circuit branch. An inter-branch circuit block between the first and second branches includes a first inter-branch transistor coupled between the first capacitor node in the first circuit branch and the fourth capacitor node in the second circuit branch and a second inter-branch transistor coupled between the third capacitor node in the second circuit branch and the second capacitor node in the first circuit branch.

Abstract: An encapsulation of laser direct structuring (LDS) material is molded onto first and second semiconductor dice. A die-to-die coupling formation between the first and second semiconductor dice includes die vias extending through the LDS material to reach the first and second semiconductor dice and a die-to-die line extending at a surface of the encapsulation between the die vias. After laser activating and structuring selected locations of the surface of the encapsulation for the die vias and die-to-die line, the locations are placed into contact with an electrode that provides an electrically conductive path. Metal material is electrolytically grown onto the locations of the encapsulation by exposure to an electrolyte carrying metal cations. The metal cations are reduced to metal material via a current flowing through the electrically conductive path provided via the electrode. The electrode is then disengaged from contact with the locations having metal material electrolytically grown thereon.

Abstract: A leadframe includes a die pad having arranged thereon a first semiconductor die with an electrically conductive ribbon extending on the first semiconductor die. The first semiconductor die lies intermediate the leadframe and the electrically conductive ribbon. A second semiconductor die is mounted on the electrically conductive ribbon to provide, on the same die pad, a stacked arrangement of the second semiconductor die and the first semiconductor die with the at least one electrically conductive ribbon intermediate the first semiconductor die and the second semiconductor die. Package size reduction can thus be achieved without appreciably affecting the assembly flow of the device.

Abstract: A pre-molded substrate for semiconductor devices includes a sculptured electrically conductive (e.g., copper) laminar structure having spaces therein. The laminar structure includes one or more die pads having a first die pad surface configured to have semiconductor chips mounted thereon. A pre-mold material molded onto the laminar structure penetrates into the spaces therein and provides a laminar pre-molded substrate including the first die pad surface left exposed by the pre-mold material with the die pad(s) bordering on the pre-mold material. One or more stress-relief curved portions are provided at the periphery of one or more of the die pads. The stress-relief curved portions are configured to border on the pre-mold material over a smooth surface to effectively counter the formation of cracks in the pre-mold material as a result of the pre-molded substrate being bent.