Abstract: Vertical dithering is performed for vertical droop compensation in image processing using Linear Feedback Shift Registers (LFSRs). Line memories are not used. A compensation circuit includes a signature reload input signal coupled to the input of five LFSRs. Each LFSR includes a signature store. The output of each LFSR provides a sequence output signal that is gated with a corresponding enable signal in a first logic circuit. The output of all of the first logic circuits are combined in a second logic circuit to provide a control signal output.

Abstract: A frame level noise estimate for an image can be determined. An image processor includes a high pass filter unit configured to perform high-pass spatial filtering of image data for first and second frames to produce high-pass spatially filtered information for the first frame and the second frame. A cumulative histogram generator is configured to analyze the high-pass spatially filtered information for the first frame and the second frame to produce a first cumulative histogram for the first frame and a second cumulative histogram for the second frame. A comparator is configured to determine a difference value between the first and second cumulative histograms. A mapping unit is configured to determine an estimated noise value based on the difference value.

Abstract: A main blind hole is formed in a front face of a wafer having a rear face. A through capacitor is formed in the main blind hole including a conductive outer electrode, a dielectric intermediate layer, and a filling conductive material forming an inner electrode. Cylindrical portions of the outer electrode, the dielectric intermediate layer and the inner electrode have front ends situated in a plane of the front face of the wafer. A secondary rear hole is formed in the rear face of the wafer to reveal a bottom of the outer electrode. A rear electrical connection is made to contact the bottom of the outer electrode through the secondary rear hole. A through hole via filled with a conductive material is provided adjacent the through capacitor. An electrical connection is made on the rear face between the rear electrical connection and the through hole via.

Abstract: A sensor array microchip apparatus includes a substrate and a lens positioned over the substrate. A plurality of radiation sensor elements are formed on the substrate in an array format and spatially separated from each other. The substrate further includes power supply circuitry (generating power for the radiation sensor elements) and processing circuitry (operable to control and process information from the radiation sensor elements). The power supply circuitry and said processing circuitry are positioned on the substrate within the array between two or more of the radiation sensor elements. The lens, in combination with the spatial separation of the radiation sensor elements in the array format, defines a relatively wide (30-80 degrees) field of regard for the sensor.

Abstract: A sporting device may include a proximity detector, and a housing for carrying the proximity detector. The proximity detector may comprise a single photon avalanche diode for measuring the speed of an object struck by the housing. For example, the housing may define a tennis racket.

Abstract: An electronic device includes a set of programming terminals for receiving corresponding programming signals, and assignment circuitry for assigning an address to the electronic device according to the programming signals. The assignment circuitry includes circuitry for providing a set of comparison signals, with at least part of the comparison signals that is variable during a non-zero comparison interval, and comparison circuitry for determining the address according to a comparison between the programming signals and the comparison signals during the comparison interval.

Abstract: A method for controlling the execution of at least one program in an electronic circuit and a processor for executing a program, in which at least one volatile memory area of the circuit is, prior to the execution of the program to be controlled, filled with first instructions resulting in an exception processing; the program contains instructions for replacing all or part of the first instructions with second valid instructions; and the area is called for execution of all or part of the instruction that it contains at the end of the execution of the instruction program.

Abstract: An embodiment of a MOS device resistant to ionizing-radiation, has: a surface semiconductor layer with a first type of conductivity; a gate structure formed above the surface semiconductor layer, and constituted by a dielectric gate region and a gate-electrode region overlying the dielectric gate region; and body regions having a second type of conductivity, formed within the surface semiconductor layer, laterally and partially underneath the gate structure. In particular, the dielectric gate region is formed by a central region having a first thickness, and by side regions having a second thickness, smaller than the first thickness; the central region overlying an intercell region of the surface semiconductor layer, set between the body regions.

Abstract: A process for assembling two parts of an integrated electronic circuit has two successive steps. During a first step, the two circuit parts are made into a single unit by molecular bonding, realized on respective application surfaces of the two parts. During a second step, electrical connections are formed from connection portions already present in the application surfaces of the two circuit parts. The connections formed extend across the bonding interface, and are compatible with a high reliability and a high level of integration of the circuit.

Abstract: An embodiment comprises a semiconductor integrated circuit for restricting the rate at which data may be accessed from an external memory by a device coupled to the circuit. The rate of data access is restricted if the data access satisfies one or more conditions. For example, one of the conditions is that the device which is requesting the data is insecure. Another condition is that the requested data is privileged. A data access monitor is provided to monitor data accesses and to is arranged to generate an access signal to indicate whether the conditions are satisfied or not. A bandwidth comparator determines whether data access exceeds a threshold and, if so, the semiconductor integrated circuit is impaired to prevent further data access.

Abstract: A filter with coupled resonator having a substrate; an acoustic mirror intended to support acoustic resonators, and to isolate these resonators from the substrate; a first structure with an upper resonator and a lower resonator coupled to one another through at least one layer of acoustic coupling; a second structure with an upper resonator and a lower resonator coupled to one another through at least one layer of acoustic coupling; the lower resonators of the first and second structure having the same electrodes. The first and second structures are connected via a fifth resonator for which electrodes and the piezoelectric layer of the lower resonators are of the first and second structure.

Abstract: A ring shaped heater surrounds a chalcogenide region along the length of a cylindrical solid phase portion thereof defining a change phase memory element. The chalcogenide region is formed in a sub-lithographic pore, so that a relatively compact structure is achieved. Furthermore, the ring contact between the heater and the cylindrical solid phase portion results in a more gradual transition of resistance versus programming current, enabling multilevel memories to be formed.

Abstract: An image sensor includes a substrate, transparent layers covering the substrate and delimiting an exposition surface exposed to light, separate photosensitive areas at the substrate level and, for each photosensitive area, a first optical means capable of deviating towards the photosensitive area light reaching a central region of a portion of the exposition surface. The sensor further includes, for each photosensitive area, a second optical means, separate from the first optical means, capable of deviating towards the photosensitive area light reaching a peripheral region of the portion of the exposition surface surrounding the central region.

Abstract: A raised source-drain structure is formed using a process wherein a semiconductor structure is received in a process chamber that is adapted to support both an etching process and an epitaxial growth process. This semiconductor structure includes a source region and a drain region, wherein the source and drain regions each include a damaged surface layer. The process chamber is controlled to set a desired atmosphere and set a desired temperature. At the desired atmosphere and temperature, the etching process of process chamber is used to remove the damaged surface layers from the source and drain regions and expose an interface surface. Without releasing the desired atmosphere and while maintaining the desired temperature, the epitaxial growth process of the process chamber is used to grow, from the exposed interface surface, a raised region above each of the source and drain regions.

Abstract: A motion estimation method is provided for processing successive images in an image sequence, with a motion vector being associated with each of the processed images. For a current image, motion vectors associated with images that precede the current image in the sequence are selected. Candidate motion vectors are generated from the motion vectors that are selected. A motion vector is elected from among the candidate motion vectors. Information that associates the elected motion vector with the current image is stored in memory. At least one of candidate motion vectors is an acceleration vector generated from the acceleration between first and second motion vectors averaged relative to a first and second images, with the first and second images being distinct and preceding the current image in the image sequence. A motion vector averaged relative to a given image is obtained from selected motion vectors associated with images preceding the given image.

Abstract: A method generates a reference voltage by steps including: generating a reference signal from a voltage source; generating a comparison signal of the reference signal with a voltage reference; sampling the comparison signal; adjusting a numerical value as a function of the result of the comparison and of the numerical value; and converting the current numerical value into a voltage corresponding to the reference voltage.

Abstract: A method for manufacturing a semiconductor chip stack device is provided. The method includes forming a first connecting element array on a surface of a first semiconductor chip; forming a second connecting element array on a surface of a second semiconductor chip, the second array comprising more connecting elements than the first array and the pitch of the first array being a multiple of the pitch of the second array; applying the first chip against the second chip; and setting up test signals between the first and second chips to determine the matching between the connecting elements of the first array and the connecting elements of the second array.

Abstract: An embodiment relates to performing error concealment of a corrupted block in a video frame, which is capable of performing a real time reconstruction of corrupted blocks which allow to precisely recover small details and fine movements, in particular, the error concealment apparatus and method according to an embodiment selects a replacement block by taking into account the luminance distortion and the motion characteristics of the video sequence. The latter is represented by the distance of the motion vectors chosen as candidate replacements and the average value of the motion vectors of the blocks surrounding the missing block in the current frame.

Abstract: An embodiment of an IGBT device is integrated in a chip of semiconductor material including a substrate of a first type of conductivity, an active layer of a second type of conductivity formed on an inner surface of the substrate, a body region of the first type of conductivity extending within the active layer from a front surface thereof opposite the inner surface, a source region of the second type of conductivity extending within the body region from the front surface, a channel region being defined within the body region between the source region and the active layer, a gate element insulated from the front surface extending over the channel region, a collector terminal contacting the substrate on a rear surface thereof opposite the inner surface, an emitter terminal contacting the source region and the body region on the front surface, and a gate terminal contacting the gate element.

Abstract: The disclosure relates to a method of fabricating an integrated circuit on a semiconductor chip, the method comprising: designing an architecture of the integrated circuit comprising at least first and second standard cells implementing a same basic function; designing for the standard cell at least first and second cell layouts presenting random differences; designing an integrated circuit layout corresponding to the integrated circuit architecture; fabricating the integrated circuit according to the integrated circuit layout; using the first cell layout to implement the first standard cell in the integrated circuit layout; and using the second cell layout to implement the second standard cell in the integrated circuit layout. The method can be used for protection of an integrated circuit against reverse engineering.