Abstract: A photodetector including a photodiode formed in a semiconductor substrate and a waveguide element formed of a block of a high-index material extending above the photodiode in a thick layer of a dielectric superposed to the substrate, the thick layer being at least as a majority formed of silicon oxide and the block being formed of a polymer of the general formula R1R2R3SiOSiR1R2R3 where R1, R2, and R3 are any carbonaceous or metal substituents and where one of R1, R2, or R3 is a carbonaceous substituent having at least four carbon atoms and/or at least one oxygen atom.

Abstract: An image sensor includes a pixel array, and a correlated double sample circuit coupled to one of the pixels in the pixel array. The correlated double sample circuit includes first and second inputs, and first and second sample capacitors respectively coupled to the first and second inputs. The first input is for receiving an analog signal from a pixel, and the second input is for receiving a time varying reference signal. The analog signal varies during a pixel readout period, and has a first level during a first reset period and a second-level during a second read period. A comparator circuit compares the time varying reference signal and the analog signal. The analog signal and the time varying reference signal are constantly read onto one of the first and second sample capacitors during both the first reset period and the second read period.

Abstract: A method of driving a sensorless brushless motor in PWM mode includes tristating a winding during a time window for detecting a zero-cross of the back electromotive force induced in the winding by rotation of a rotor, monitoring voltage of the tristated winding during an unmasked portion of the time window, and detecting during the time window a zero-cross event of the induced back electromotive force. The method includes verifying whether the zero-cross event occurred during the unmasked portion, modifying for the next cycle the duration of the time window and/or of the unmasked portion thereof based upon the verification, defining a safety interval in the unmasked time window, modifying the duration of the time window and/or of the unmasked portion thereof depending on whether the zero-cross event has been detected during the safety interval.

Abstract: Transcoder apparatus for transcoding an input video bit-stream having a first encoding profile (e.g., MPEG-2) into an output video bit-stream having a second encoding profile (e.g., H.264), the first encoding profile including motion estimation information, the apparatus including: a front-end for extracting the motion estimation information from the input video bit-stream, and a back-end for constructing the output bit-stream. The front-end and the back-end of the apparatus are interconnected (e.g., via a buffer) to pass the motion estimation information from the front-end to the back-end, thereby avoiding motion estimation in constructing the output bit-stream at the apparatus back-end.

Abstract: A first base station is adjacent to one or more second base stations, and the second base stations are adjacent to one or more third base stations. One or more frequency channels or subframes used by the third base stations are identified by the second base stations, which notify the first base station of the frequency channels or subframes used by the third base stations. The second base stations also notify the first base station of the frequency channels or subframes used by the second base stations. The first base station selects a working frequency channel or subframe based on this information. For example, the first base station may ignore any frequency channels or subframes used by the adjacent second base stations. The first base station may also give priority to the frequency channels or subframes used by the non-adjacent third base stations.

Abstract: An analog switch includes a transistor whose source connected to a signal input and whose drain is connected to a signal output. An output of a gate control circuit is connected to the transistor gate. A first input of the gate control circuit is connected to the source of the transistor. The gate control circuit responds to a logic transition of an enable signal received at a second input by pre-charging a substantially constant gate-to-source voltage across the transistor. This voltage is stored by a gate-to-source connected capacitor. In one steady-state logic condition of the enable signal, the gate control circuit operates to turn off the transistor. In another steady-state logic condition of the enable signal, the gate control circuit permits the signal received at the signal input to drive the gate of the transistor with a voltage offset by the substantially constant gate-to-source voltage stored on the capacitor.

Abstract: A test circuit is described of a circuit integrated on wafer of the type comprising at least one antenna of the embedded type comprising at least one test antenna associated with said at least one embedded antenna that realizes its connection of the wireless loopback type creating a wireless channel for said at least one embedded antenna and allows its electric test, transforming an electromagnetic signal of communication between said at least one embedded antenna and said at least one test antenna into an electric signal that can be read by a test apparatus.

Abstract: A multi-threshold complementary metal-oxide semiconductor technology (MTCMOS technology) master slave flip-flop with a single clock signal includes a master storage element configured to store an input data in response to a clock signal transition and a slave storage element configured to receive data from the master storage element and to output the received data in response to an opposite clock signal transition. The master storage element includes low threshold voltage transistors, the slave storage element includes high threshold voltage transistors, and the master and the slave storage elements are provided with a single clock signal.

Abstract: A system for testing faults in shadow logic includes a sequential block coupled to a shadow logic block and a delaying block to receive test patterns for testing the shadow logic block. The delaying block delays the test patterns by an access time of the sequential block to generate delayed test patterns. The delayed test patterns are passed to the shadow logic block for testing faults.

Abstract: A device for detecting a fault attack, including: a circuit for detecting an interruption of a power supply; a circuit for comparing the duration of said interruption with a first threshold; and a counter of the number of successive interruptions of the power supply having a duration which does not exceed the first threshold.

Abstract: Embodiment of a system for generating electric power with micro fuel cells comprising at least one first micro cell and at least one second micro cell, each micro cell having an anode and a cathode with a membrane being sandwich-wise interposed, the system comprising a spacer element having an annular element that surrounds a cavity, said spacer element being associated with said anode of said first micro cell and with said anode of said second micro cell to realize a common diffusion chamber for the fuel of said first micro cell a of said second micro cell.

Abstract: There is described a protection apparatus against electrostatic discharges for an integrated circuit; said integrated circuit comprises a radiofrequency or higher frequencies internal circuit. The internal circuit has a first and a second terminals for the output or the input of a radiofrequency or higher frequencies signal. The apparatus comprises first means for electrically connecting said first and second terminals of the internal circuit to at least a PAD and the integrated circuit comprises at least a first and a second supply circuital lines and at least a first and a second protection devices against electrostatic discharges connected to said first and second supply lines. First means have a resistive component and each of said first and second protection devices against the electrostatic discharges have a parasitic capacitive component.

Abstract: An electrically programmable non-volatile memory device is proposed. The memory device includes a plurality of memory cells and a driver circuit for driving the memory cells; the driver circuit includes programming means for providing a first programming voltage and a second programming voltage to a set of selected memory cells for programming the selected memory cells; the first programming voltage requires a first transient period for reaching a first target value thereof. In the solution according to an embodiment of the present invention, the programming means includes means for maintaining the second programming voltage substantially equal to the first programming voltage during a second transient period being required by the second programming voltage to reach a second target value thereof.

Abstract: A device for correlating trend data with respect to a patient's weight ankle displacement can identify conditions indicative of congestive heart failure. A weight scale or similar device coupled with imaging mechanism operable to measure ankle displacement collects a plurality of measurements over a period of time. Over time trend analysis of both the patient's weight and the ankle displacement measurements can be obtained and compared to identify whether over a particular sample period an increase in a patient's ankle displacement is or is not correlated with an increase in the patient's weight. When an increase in ankle displacement is identified as not correlating to a corresponding change in the patient's weight an alert can be issued of conditions indicative of congestive heart failure.

Abstract: A process for connecting two bodies forming parts of an electromechanical, fluid and optical microsystem, wherein a welding region is formed on a first body; an electrically conductive region and a spacing region are formed on a second body; the spacing region extends near the electrically conductive region and has a height smaller than the electrically conductive region. One of the first and second bodies is turned upside down on the other, and the two bodies are welded together by causing the electrically conductive region to melt so that it adheres to the welding region and collapses until its height becomes equal to that of the spacing region. Thereby it is possible to seal active parts or micromechanical structures with respect to the outside world, self-align the two bodies during bonding, obtain an electrical connection between the two bodies, and optically align two optical structures formed on the two bodies.

Abstract: One embodiment is a phase change memory that includes a heater element transversely contacting a storage element of phase change material. In particular, an end of the storage element contacts an end of the heater element. A first pair of dielectric spacers is positioned on opposite sides of the first heater element and a second pair of dielectric spacers is positioned on opposite sides of the first storage element. The storage element, heater element, and first and second pairs of dielectric spacers can be made by a spacer patterning technique.

Abstract: An integrated circuit of the type comprises a plurality of units that may act as initiators and targets. At least some of the units are for a first purpose such as a cable modem function and others are for a second purpose such as television data processing. The units are connected together by a interconnect comprising a number of nodes. One of the nodes is configurable such that requests made from initiator units on one side of the node to target units on the other side of the node are not sent to the target units. The units for the first purpose are arranged on the opposite side of the node from those of the second purpose, so that the circuit is effectively configurable into two separate logical partitions, one partition for television data processing and the other partition for cable modem functions.

Abstract: The method is for transmitting data between two devices via a clock wire or line and at least one data wire or line. The clock wire is maintained by default on a logic value A, and each device is capable of tying the clock wire to an electric potential representing a logic value B that is the opposite of A. According to the method, both devices tie the clock wire to B when a datum is transmitted, the device to which the datum is sent does not release the clock wire while it has not read the datum, and the device sending the datum maintains the datum on the data wire at least until an instant when the clock wire is released by the device to which the datum is sent. The method is particularly applicable to communication between a microcomputer and a microprocessor.

Abstract: The method of processing a first digital image by combining the first digital image with a second digital image includes the first digital image being received from a pixel array, and when receiving the first digital image it is converted into a first continuous sequential data stream. The second digital image may be provided in the form of a second continuous sequential data stream, and the first and second digital images may be combined by continuously combining the data in the first and second data stream.

Abstract: A memory element for a magnetic RAM, having a first magnetic portion in a first recess of a first insulating layer; and a non-magnetic portion and a second magnetic portion in a second recess of a second insulating layer covering the first insulating layer, the second recess exposing the first magnetic portion and a portion of the first insulating layer around the first magnetic portion, the non-magnetic portion being interposed between the first and second magnetic portions.