Patents Assigned to STMicroelectronics (Beijing) R&D Co. Ltd.
  • Patent number: 10970192
    Abstract: A debug-enabled processing device includes a processor, a communication transceiver circuit, and a debug support unit. The debug support unit has a plurality of dedicated debug registers to facilitate debugging a software program under execution by the processor. One of the plurality of debug registers is a control register having at least four bits, which are used to enable/disable a plurality of debugging operations. Others of the debug registers include a set of index registers that may be configured to pass data to and from the processor.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: April 6, 2021
    Assignee: STMICROELECTRONICS (BEIJING) R&D CO. LTD
    Inventors: Xiao Kang Jiao, PengFei Zhu
  • Patent number: 10883828
    Abstract: An embodiment comprises and apparatus having an image capture device with an image axis and a gyroscope operable to indicate the orientation of the image axis. An embodiment of a capsule endoscopy system comprises an imaging capsule and an external unit. The imaging capsule may comprise an image capture device having an image axis and a gyroscope operable to indicate the orientation of the image axis. The external unit may comprise a gyroscope operable to indicate an orientation of a subject and a harness wearable by a subject and operable to align the gyroscope with the subject. The imaging capsule may send and image to an external unit for processing and display, and the external unit may provide for calculation of the image-axis orientation relative to the body.
    Type: Grant
    Filed: July 10, 2017
    Date of Patent: January 5, 2021
    Assignee: STMICROELECTRONICS (BEIJING) R&D CO., LTD
    Inventors: Peng Fei Zhu, Yong Qiang Wu, Kai Feng Wang, Hong Xia Sun
  • Patent number: 10877238
    Abstract: Embodiments are directed to devices and methods including a time-of-flight sensor and a camera. In one embodiment, a device is provided that includes a time-of-flight sensor, distance estimation circuitry, a camera, and processing circuitry. The time-of-flight sensor transmits an optical pulse signal and receives return optical pulse signals corresponding to portions of the transmitted optical pulse signal reflected by an object. The distance estimation circuitry estimates a minimum distance to the object based on a time between transmitting the optical pulse signal and receiving a first portion of the return optical pulse signals, and estimates a maximum distance to the object based on a time between transmitting the optical pulse signal and receiving a second portion of the return optical pulse signals. The processing circuitry controls a focus distance and an aperture setting of the camera based on the estimated minimum and maximum distances to the object.
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: December 29, 2020
    Assignee: STMICROELECTRONICS (BEIJING) R&D CO. LTD
    Inventor: Yong Li
  • Patent number: 10686392
    Abstract: The present disclosure is directed to a permanent magnet motor control method and system. A new structure configuration of a permanent magnet motor has a rotor with two or more permanent magnets attached thereon, a stator wound in a “Y” topology with three coils (windings) arranged at 120 degree among one another, and a neutral point of the wound stator wired in a manner that the voltage at the neutral point may be detected in substantially real time. The detected neutral point voltages are analyzed together with the associated vectors of the excitation current provided to the windings of the stator to determine a speed of the rotor. The determined speed of the rotor is used for vector control.
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: June 16, 2020
    Assignee: STMICROELECTRONICS (BEIJING) R&D CO. LTD.
    Inventor: Rendong Wang
  • Patent number: 10620760
    Abstract: A method includes upon sensing a touch to a first location on a touch display, reporting first coordinates of the touch. After sensing movement of the touch along a first path from the first location to a second location more than a tolerance distance away, intermediate coordinates of the touch along the first path that are not more than a cutoff distance away are reported such that there is a first gap between a last reported intermediate coordinate and the second location. After sensing movement of the touch along a second path from the second location to a third location more, second coordinates of the touch are reported, the second reported coordinates of the touch being a point along the first path that is calculated by subtracting the first gap from a distance between the first location and the third location, and then adding a first compensation difference thereto.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: April 14, 2020
    Assignees: STMicroelectronics (Beijing) R&D Co. Ltd, STMicroelectronics Asia Pacific Pte Ltd
    Inventors: Hang Yin, Cam Chung La, Janet Sun
  • Patent number: 10296441
    Abstract: A debug-enabled processing device includes a processor, a communication transceiver circuit, and a debug support unit. The debug support unit has a plurality of dedicated debug registers to facilitate debugging a software program under execution by the processor. One of the plurality of debug registers is a control register having at least four bits, which are used to enable/disable a plurality of debugging operations. Others of the debug registers include a set of index registers that may be configured to pass data to and from the processor.
    Type: Grant
    Filed: July 6, 2016
    Date of Patent: May 21, 2019
    Assignee: STMICROELECTRONICS (BEIJING) R&D CO. LTD
    Inventors: Xiao Kang Jiao, PengFei Zhu
  • Publication number: 20190113999
    Abstract: A method includes upon sensing a touch to a first location on a touch display, reporting first coordinates of the touch. After sensing movement of the touch along a first path from the first location to a second location more than a tolerance distance away, intermediate coordinates of the touch along the first path that are not more than a cutoff distance away are reported such that there is a first gap between a last reported intermediate coordinate and the second location. After sensing movement of the touch along a second path from the second location to a third location more, second coordinates of the touch are reported, the second reported coordinates of the touch being a point along the first path that is calculated by subtracting the first gap from a distance between the first location and the third location, and then adding a first compensation difference thereto.
    Type: Application
    Filed: November 3, 2017
    Publication date: April 18, 2019
    Applicants: STMicroelectronics (Beijing) R&D Co. Ltd, STMicroelectronics Asia Pacific Pte Ltd
    Inventors: Hank Yin, Cam Chung La, Janet Sun
  • Patent number: 10114644
    Abstract: A decoding logic method is arranged to execute a zero-overhead loop in an embedded digital signal processor (DSP). In the method, instruction data is fetched from a memory, and a plurality of instruction tokens, which are derived from the instruction data, are stored in a token buffer. A first portion of one or more instruction tokens from the token buffer are passed to a first decode module, which may be an instruction decode module, and a second portion of the one or more instruction tokens from the token buffer are passed to a second decode module, which may be a loop decode module. The second decode module detects a special loop instruction token, and based on the detection of the special loop instruction token, a loop counter is conditionally tested. Using the first decode module, at least one instruction token of an iterative algorithm is assembled into a single instruction, which is executable in a single execution cycle.
    Type: Grant
    Filed: July 26, 2016
    Date of Patent: October 30, 2018
    Assignee: STMICROELECTRONICS (BEIJING) R&D CO. LTD
    Inventors: PengFei Zhu, Xiao Kang Jiao
  • Patent number: 9977445
    Abstract: An electronic device disclosed herein includes a linear output stage configured to generate an output voltage to an output node as a function of an input voltage, and a buck output stage configured to generate the output voltage to the output node as a function of the input voltage. Control circuitry is configured to enable the linear output stage and disable the buck output stage if a current demanded by a load to maintain the output voltage at a desired level is less than a limit current, and enable the buck output stage and disable the linear output stage a delay period of time after enabling the buck output stage, if the current demanded by the load to maintain the output voltage at the desired level is greater than the limit current.
    Type: Grant
    Filed: February 23, 2016
    Date of Patent: May 22, 2018
    Assignee: STMicroelectronics (Beijing) R&D Co. Ltd
    Inventor: Zhenghao Cui
  • Patent number: 9813051
    Abstract: An electronic circuit is for switching a power transistor having a drain coupled to a drain node, a source coupled to a lower voltage supply, and a gate coupled to a gate node. The electronic circuit includes first current generation circuitry to generate a first current to flow into the gate node in response to assertion off an ON signal, the first current being substantially constant. Second current generation circuitry generates a second current to flow into the gate node in response to deassertion of an OFF signal, the second current being inversely proportional to a gate to source voltage of the power transistor. First comparison circuitry compares a drain voltage at the drain node to a reference voltage, and activates third current generation circuitry to generate a third current to flow into the gate node when the drain voltage is less than the reference voltage.
    Type: Grant
    Filed: February 24, 2016
    Date of Patent: November 7, 2017
    Assignee: STMicroelectronics (Beijing) R&D Co. Ltd
    Inventor: Zhenghao Cui
  • Publication number: 20170308220
    Abstract: An electronic device described herein includes a touch screen for a touch sensitive display carried by a portable housing. The electronic device is configured to operate in a high. detection threshold mode to determine whether an object is in contact with the touch sensitive display, and operate in a low detection threshold mode to determine whether the object is adjacent to the touch sensitive display, based on lack of detection of the object being in contact with the touch sensitive display. The electronic device is further configured to determine whether the object is in contact with a peripheral edge of the portable housing by determining whether the object is adjacent opposite sides of the touch sensitive display, based on detection of the object being adjacent to the touch sensitive display.
    Type: Application
    Filed: May 10, 2016
    Publication date: October 26, 2017
    Applicants: STMicroelectronics Asia Pacific Pte Ltd, STMicroelectronics (Beijing) R&D Co. Ltd
    Inventors: Tae-gil Kang, Hang Yin, Cam Chung La
  • Publication number: 20170237421
    Abstract: An electronic circuit is for switching a power transistor having a drain coupled to a drain node, a source coupled to a lower voltage supply, and a gate coupled to a gate node. The electronic circuit includes first current generation circuitry to generate a first current to flow into the gate node in response to assertion off an ON signal, the first current being substantially constant. Second current generation circuitry generates a second current to flow into the gate node in response to deassertion of an OFF signal, the second current being inversely proportional to a gate to source voltage of the power transistor. First comparison circuitry compares a drain voltage at the drain node to a reference voltage, and activates third current generation circuitry to generate a third current to flow into the gate node when the drain voltage is less than the reference voltage.
    Type: Application
    Filed: February 24, 2016
    Publication date: August 17, 2017
    Applicant: STMicroelectronics (Beijing) R&D Co. Ltd
    Inventor: Zhenghao Cui
  • Publication number: 20170235321
    Abstract: An electronic device disclosed herein includes a linear output stage configured to generate an output voltage to an output node as a function of an input voltage, and a buck output stage configured to generate the output voltage to the output node as a function of the input voltage. Control circuitry is configured to enable the linear output stage and disable the buck output stage if a current demanded by a load to maintain the output voltage at a desired level is less than a limit current, and enable the buck output stage and disable the linear output stage a delay period of time after enabling the buck output stage, if the current demanded by the load to maintain the output voltage at the desired level is greater than the limit current.
    Type: Application
    Filed: February 23, 2016
    Publication date: August 17, 2017
    Applicant: STMicroelectronics (Beijing) R&D Co. Ltd
    Inventor: Zhenghao Cui
  • Patent number: 9170817
    Abstract: Some microprocessors check branch prediction information in a branch history table and/or a branch target buffer. To check for branch prediction information, a microprocessor can identify which instructions are control flow instructions and which instructions are non control flow instructions. To reduce power consumption in the branch history table and/or branch target buffer, the branch history table and/or branch target buffer can check for branch prediction information corresponding to the control flow instructions and not the non control flow instructions.
    Type: Grant
    Filed: August 4, 2009
    Date of Patent: October 27, 2015
    Assignee: STMicroelectronics (Beijing) R&D Co., Ltd.
    Inventors: Kai-Feng Wang, Hong-Xia Sun, Yong-Qiang Wu
  • Patent number: 9015450
    Abstract: Embodiments of a processor architecture efficiently implement shadow registers in hardware. A register system in a processor includes a set of physical data registers coupled to register renaming logic. The register renaming logic stores data in and retrieves data from the set of physical registers when the processor is in a first processor state. The register renaming logic identifies ones of the set of physical registers that have a first operational state as a first group of registers and identifies the remaining ones of the set of physical registers as a second group of registers in response to an indication that the processor is to enter a second processor state from the first processor state. The register renaming logic stores data in and retrieves data from the second group of registers but not the first group of registers when the processor is in the second processor state.
    Type: Grant
    Filed: January 20, 2010
    Date of Patent: April 21, 2015
    Assignee: STMicroelectronics (Beijing) R&D Co. Ltd.
    Inventors: Hong-Xia Sun, Peng Fei Zhu, Yong Qiang Wu
  • Patent number: 9014284
    Abstract: In an embodiment, a transmitter includes first and second processing blocks, which may each include hardware, software, or a combination of hardware and software. The first processing block is operable to generate a first peak-reducing vector. And the a second first processing block is operable to receive a first data vector, the data vector comprising a plurality of samples, the first data vector having a first peak with a first index and a first magnitude, a second peak with a second index and a second magnitude that is less than the first magnitude, and a first peak-to-average power ratio, and to generate a second data vector having a second peak-to-average power ratio that is lower than the first peak-to-average power ratio by using the first peak-reducing vector.
    Type: Grant
    Filed: August 23, 2013
    Date of Patent: April 21, 2015
    Assignee: STMicroelectronics (Beijing) R&D Co. Ltd.
    Inventor: Sen Jiang
  • Patent number: 8953497
    Abstract: In mesh networks having multiple nodes that communicate data to and from each other, a great number of data transmissions may be initiated and carried out to get data to a proper processing node for execution. To get data where it needs to go (e.g., the proper destination node), a routing algorithm is used to define a set of rules for efficiently passing data from node to node until the destination node is reached. For the purpose of assuring that all data is properly transferred from node to node in a reasonably efficient manner, a routing algorithm may define subsets of nodes into regions and then send data via the regions. Even greater overall efficiency may be realized by recognizing specific adjacency relationships among a group of destination nodes and taking advantage of such adjacencies by rerouting data through regions other than the region in which a destination node resides.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: February 10, 2015
    Assignee: STMicroelectronics (Beijing) R&D Co. Ltd.
    Inventors: Kai Feng Wang, PengFei Zhu, HongXia Sun, YongQiang Wu
  • Publication number: 20140122837
    Abstract: Embodiments of a processor architecture utilizing multi-bank implementation of physical register mapping table are provided. A register renaming system to correlate architectural registers to physical registers includes a physical register mapping table and a renaming logic. The physical register mapping table has a plurality of entries each indicative of a state of a respective physical register. The mapping table has a plurality of non-overlapping sections each of which having respective entries of the mapping table. The renaming logic is coupled to search a number of the sections of the mapping table in parallel to identify entries that indicate the respective physical registers have a first state. The renaming logic selectively correlates each of a plurality of architectural registers to a respective physical register identified as being in the first state. Methods of utilizing the multi-bank implementation of physical register mapping table are also provided.
    Type: Application
    Filed: October 28, 2013
    Publication date: May 1, 2014
    Applicant: STMicroelectronics (Beijing) R&D Co. Ltd.
    Inventors: Peng Fei Zhu, Hong-Xia Sun, Yong Qiang Wu
  • Patent number: 8681742
    Abstract: A mobile device includes a communications protocol stack including a MAC layer and TCP layer separated by an IP layer. A cross-layer coordination module parallel to the communications protocol stack is coupled to both the MAC layer and TCP layer. The MAC layer generates a message sent to the cross-layer coordination module indicating that the mobile device is about to engage in a communications handover from a first base station to a second base station. The cross-layer coordination module passes handover information to the TCP layer so as to inform the TCP layer of the communications handover. If the mobile device is operating as a TCP sender, the TCP layer freezes its connection and state during the communications handover. If the mobile device is operating as a TCP receiver, the TCP layer sends a TCP ACK message to a TCP sender having an advertised window size set to a zero value so as to cause the TCP sender to freeze a connection and state during communications handover.
    Type: Grant
    Filed: June 23, 2011
    Date of Patent: March 25, 2014
    Assignee: STMicroelectronics (Beijing) R&D Co., Ltd.
    Inventors: Guobin Sun, Hongfei Zhu, Yanling Yao
  • Publication number: 20130343482
    Abstract: In an embodiment, a transmitter includes first and second processing blocks, which may each include hardware, software, or a combination of hardware and software. The first processing block is operable to generate a first peak-reducing vector. And the a second first processing block is operable to receive a first data vector, the data vector comprising a plurality of samples, the first data vector having a first peak with a first index and a first magnitude, a second peak with a second index and a second magnitude that is less than the first magnitude, and a first peak-to-average power ratio, and to generate a second data vector having a second peak-to-average power ratio that is lower than the first peak-to-average power ratio by using the first peak-reducing vector.
    Type: Application
    Filed: August 23, 2013
    Publication date: December 26, 2013
    Applicant: STMicroelectronics (Beijing) R&D Co., Ltd.
    Inventor: Sen JIANG