Abstract: Some microprocessors check branch prediction information in a branch history table and/or a branch target buffer. To check for branch prediction information, a microprocessor can identify which instructions are control flow instructions and which instructions are non control flow instructions. To reduce power consumption in the branch history table and/or branch target buffer, the branch history table and/or branch target buffer can check for branch prediction information corresponding to the control flow instructions and not the non control flow instructions.

Abstract: Embodiments of a processor architecture efficiently implement shadow registers in hardware. A register system in a processor includes a set of physical data registers coupled to register renaming logic. The register renaming logic stores data in and retrieves data from the set of physical registers when the processor is in a first processor state. The register renaming logic identifies ones of the set of physical registers that have a first operational state as a first group of registers and identifies the remaining ones of the set of physical registers as a second group of registers in response to an indication that the processor is to enter a second processor state from the first processor state. The register renaming logic stores data in and retrieves data from the second group of registers but not the first group of registers when the processor is in the second processor state.

Abstract: In an embodiment, a transmitter includes first and second processing blocks, which may each include hardware, software, or a combination of hardware and software. The first processing block is operable to generate a first peak-reducing vector. And the a second first processing block is operable to receive a first data vector, the data vector comprising a plurality of samples, the first data vector having a first peak with a first index and a first magnitude, a second peak with a second index and a second magnitude that is less than the first magnitude, and a first peak-to-average power ratio, and to generate a second data vector having a second peak-to-average power ratio that is lower than the first peak-to-average power ratio by using the first peak-reducing vector.

Abstract: In mesh networks having multiple nodes that communicate data to and from each other, a great number of data transmissions may be initiated and carried out to get data to a proper processing node for execution. To get data where it needs to go (e.g., the proper destination node), a routing algorithm is used to define a set of rules for efficiently passing data from node to node until the destination node is reached. For the purpose of assuring that all data is properly transferred from node to node in a reasonably efficient manner, a routing algorithm may define subsets of nodes into regions and then send data via the regions. Even greater overall efficiency may be realized by recognizing specific adjacency relationships among a group of destination nodes and taking advantage of such adjacencies by rerouting data through regions other than the region in which a destination node resides.

Abstract: Embodiments of a processor architecture utilizing multi-bank implementation of physical register mapping table are provided. A register renaming system to correlate architectural registers to physical registers includes a physical register mapping table and a renaming logic. The physical register mapping table has a plurality of entries each indicative of a state of a respective physical register. The mapping table has a plurality of non-overlapping sections each of which having respective entries of the mapping table. The renaming logic is coupled to search a number of the sections of the mapping table in parallel to identify entries that indicate the respective physical registers have a first state. The renaming logic selectively correlates each of a plurality of architectural registers to a respective physical register identified as being in the first state. Methods of utilizing the multi-bank implementation of physical register mapping table are also provided.

Abstract: A mobile device includes a communications protocol stack including a MAC layer and TCP layer separated by an IP layer. A cross-layer coordination module parallel to the communications protocol stack is coupled to both the MAC layer and TCP layer. The MAC layer generates a message sent to the cross-layer coordination module indicating that the mobile device is about to engage in a communications handover from a first base station to a second base station. The cross-layer coordination module passes handover information to the TCP layer so as to inform the TCP layer of the communications handover. If the mobile device is operating as a TCP sender, the TCP layer freezes its connection and state during the communications handover. If the mobile device is operating as a TCP receiver, the TCP layer sends a TCP ACK message to a TCP sender having an advertised window size set to a zero value so as to cause the TCP sender to freeze a connection and state during communications handover.

Abstract: In an embodiment, a transmitter includes first and second processing blocks, which may each include hardware, software, or a combination of hardware and software. The first processing block is operable to generate a first peak-reducing vector. And the a second first processing block is operable to receive a first data vector, the data vector comprising a plurality of samples, the first data vector having a first peak with a first index and a first magnitude, a second peak with a second index and a second magnitude that is less than the first magnitude, and a first peak-to-average power ratio, and to generate a second data vector having a second peak-to-average power ratio that is lower than the first peak-to-average power ratio by using the first peak-reducing vector.

Abstract: Embodiments of a processor architecture utilizing multi-bank implementation of physical register mapping table are provided. A register renaming system to correlate architectural registers to physical registers includes a physical register mapping table and a renaming logic. The physical register mapping table has a plurality of entries each indicative of a state of a respective physical register. The mapping table has a plurality of non-overlapping sections each of which having respective entries of the mapping table. The renaming logic is coupled to search a number of the sections of the mapping table in parallel to identify entries that indicate the respective physical registers have a first state. The renaming logic selectively correlates each of a plurality of architectural registers to a respective physical register identified as being in the first state. Methods of utilizing the multi-bank implementation of physical register mapping table are also provided.

Abstract: In an embodiment, a transmitter includes first and second processing blocks, which may each include hardware, software, or a combination of hardware and software. The first processing block is operable to generate a first peak-reducing vector. And the a second first processing block is operable to receive a first data vector, the data vector comprising a plurality of samples, the first data vector having a first peak with a first index and a first magnitude, a second peak with a second index and a second magnitude that is less than the first magnitude, and a first peak-to-average power ratio, and to generate a second data vector having a second peak-to-average power ratio that is lower than the first peak-to-average power ratio by using the first peak-reducing vector.

Abstract: A technique for selecting instructions for execution from an issue queue at multiple function units while reducing the chances of instruction collisions. In an embodiment, each function unit in a processor may include a selection logic circuit that selects a specific instruction from the issue queue for execution. In order to avoid instruction collision, a function unit may have a selection logic circuit that may select two instructions from an instruction queue: one according to a first selection technique and one according to a second selection technique. Then, by comparing the instruction selected by the first selection technique to the instruction selected by the selection logic circuit of another function unit, the instruction selected by the second technique may be used instead if there will be an instruction collision because the instruction selected by the first selection technique is the same as the instruction selected at a different function unit.

Abstract: According to an embodiment, a receiver, system and method for channel estimation in a communications system utilizing multiple transmit antennas are provided. The receiver comprises an antenna node operable to receive a signal that includes a superposition of at least a first signal corresponding to a first sequence and a second signal corresponding to a second sequence; and a channel estimator, coupled to the antenna node, operable to correlate the received signal with at least one of the first and second sequences, to determine at least one boundary between at least two waveforms resulting from the correlation, and to calculate using the boundary and the at least two waveforms a first channel response corresponding to the first signal and a second channel response corresponding the second signal. Channel estimates are determined based on determined boundaries and may be smoothed by a Savitzky-Golay filter in the frequency domain. The variance of additive white Gaussian noise (AWGN) may also be estimated.

Abstract: A system for recovering an architecture register mapping table (ARMT). The system includes a first number of collection circuits and decode circuits, a second number of selection circuits, and an enable circuit. Information related to the mapping between each physical register and an appropriate architecture register is obtained from a physical register mapping table (PRMT) by one and only one collection circuit during only one of a fourth number of instruction cycles. Each decode circuit has its input coupled to the output of one different collection circuit and is capable of converting its input into a third number bit wide binary string selection code at its output. Each selection circuit is configured to receive from each selection code a bit from a bit position associated with that selection circuit. The enable circuit is configured to appropriately enable mapping of information from the PRMT to the ARMT.

Abstract: A comparison circuit can reduce the amount of power consumed when searching a load queue or a store queue of a microprocessor. Some embodiments of the comparison circuit use a comparison unit that performs an initial comparison of addresses using a subset of the address bits. If the initial comparison results in a match, a second comparison unit can be enabled to compare another subset of the address bits.

Abstract: A database stores updated information concerning protected communications services. A base station for a coexisting, and potentially co-channel, non-protected communications service makes an inquiry of the database requesting an identification of geographically relevant protected services along with the database stored information pertinent to each of those identified protected services. The returned information is processed by the base station to determine what channels are available for use by the non-protected service. An available channel is identified by the base station as the working channel for the non-protected service and the base station initiates a process to establish a communications network using the non-protected service and the selected working channel.

Abstract: In mesh networks having multiple nodes that communicate data to and from each other, a great number of data transmissions may be initiated and carried out to get data to a proper processing node for execution. To get data where it needs to go (e.g., the proper destination node), a routing algorithm is used to define a set of rules for efficiently passing data from node to node until the destination node is reached. For the purpose of assuring that all data is properly transferred from node to node in a reasonably efficient manner, a routing algorithm may define subsets of nodes into regions and then send data via the regions. Even greater overall efficiency may be realized by recognizing specific adjacency relationships among a group of destination nodes and taking advantage of such adjacencies by rerouting data through regions other than the region in which a destination node resides.

Abstract: In a network-on-chip (NoC) system, multiple data messages may be transferred among modules of the system. Power consumption due to the transfer of the messages may affect a cost and overall performance of the system. A described technique provides a way to reduce a volume of data transferred in the NoC system by exploiting redundancy of data messages. Thus, if a data message to be sent from a source in the NoC includes so-called “zero” bytes that are bytes including only bits set to “0,” such zero bytes may not be transmitted in the NoC. Information on whether each byte of the data message is a zero byte may be recorded in a storage such as a data structure. This information, together with non-zero bytes of the data message, may form a compressed version of the data message. The information may then be used to uncompress the compressed data message at a destination.

Abstract: A database stores updated information concerning protected communications services. A base station for a coexisting, and potentially co-channel, non-protected communications service makes an inquiry of the database requesting an identification of geographically relevant protected services along with the database stored information pertinent to each of those identified protected services. The returned information is processed by the base station to determine what channels are available for use by the non-protected service. An available channel is identified by the base station as the working channel for the non-protected service and the base station initiates a process to establish a communications network using the non-protected service and the selected working channel.

Abstract: A database stores updated information concerning protected communications services. A base station for a coexisting, and potentially co-channel, non-protected communications service makes an inquiry of the database requesting an identification of geographically relevant protected services along with the database stored information pertinent to each of those identified protected services. The returned information is processed by the base station to determine what channels are available for use by the non-protected service. An available channel is identified by the base station as the working channel for the non-protected service and the base station initiates a process to establish a communications network using the non-protected service and the selected working channel.

Abstract: A mobile device includes a communications protocol stack including a MAC layer and TCP layer separated by an IP layer. A cross-layer coordination module parallel to the communications protocol stack is coupled to both the MAC layer and TCP layer. The MAC layer generates a message sent to the cross-layer coordination module indicating that the mobile device is about to engage in a communications handover from a first base station to a second base station. The cross-layer coordination module passes handover information to the TCP layer so as to inform the TCP layer of the communications handover. If the mobile device is operating as a TCP sender, the TCP layer freezes its connection and state during the communications handover. If the mobile device is operating as a TCP receiver, the TCP layer sends a TCP ACK message to a TCP sender having an advertised window size set to a zero value so as to cause the TCP sender to freeze a connection and state during communications handover.

Abstract: According to an embodiment, a receiver, system and method for channel estimation in a communications system utilizing multiple transmit antennas are provided. The receiver comprises an antenna node operable to receive a signal that includes a superposition of at least a first signal corresponding to a first sequence and a second signal corresponding to a second sequence; and a channel estimator, coupled to the antenna node, operable to correlate the received signal with at least one of the first and second sequences, to determine at least one boundary between at least two waveforms resulting from the correlation, and to calculate using the boundary and the at least two waveforms a first channel response corresponding to the first signal and a second channel response corresponding the second signal. Channel estimates are determined based on determined boundaries and may be smoothed by a Savitzky-Golay filter in the frequency domain. The variance of additive white Gaussian noise (AWGN) may also be estimated.