Abstract: The present description discloses a secure element and a communication method, configured to implement at least one first application, and including a circuit configured to record routing data and a list and parameters of communication protocols compatible with the first application, verify the compatibility of a first communication protocol used by first messages intended for the first application with the protocols of the list, convert the first messages into second messages by using a second communication protocol in response to the first protocol not being compatible with at least one of the protocols of the list, and direct the second messages to the first application by using the routing data of the first application.

Abstract: A device includes a memory, a first firmware copy of the device stored in a first position of the memory and a second firmware copy of the device stored in a second position of the memory, where each of the first firmware copy and the second firmware copy includes instructions, when executed by the device, perform an operation of the device; and a first delta copy associated with the first firmware copy. The first delta copy includes instructions that differ from the first firmware copy when executed at the first position and are the same when executed at the second position. The device is configured to receive the first delta copy from an external system and store the first delta copy in the memory.

Abstract: The present disclosure relates to authenticating a first device to a second device, including at least two successive verification operations comprising the following successive steps. The second device generates a first data, and sends the first data to the first device. The first device generates a third data and a fourth data used by the following verification operation and sends the third data to the second device. The second device checks the third data indicating whether the check was successful or not.

Abstract: A memory system for use with a master-slave type bus such as an AHB bus has a memory, a bus interface to allow memory access from the bus, and a direct memory access interface to allow memory access from a DMA controller without occupying the bus. The system can reduce occupancy of the bus, it can allow dedicated DMA access protocols faster than the bus protocol to be used, and can remove or reduce the need for bus arbitration and associated circuitry and delays. An arbiter can arbitrate between the memory accesses and give priority to DMA accesses.

Abstract: A code patching device is provided for use with a processor having a read-only memory which stores instruction code and a further memory for storing patch code. A plurality of patch address registers each store an address, in the read-only memory, at which a patch is to be performed. A comparator compares the address of the read-only memory that is being accessed by the processor with the addresses stored in the registers. A control unit selects between code from the read-only memory or patch code from the further memory depending on the comparison. The code patching device can replace, on-the-fly, erroneous lines of code from the read-only memory by corrected ones. During an initialization process the patch code is loaded into the further memory and the registers are loaded with the addresses which require patching.

Abstract: A receive path in a receiver including circuitry for deriving a first stream of first digitized samples from a received analog signal at a first sampling rate, and at least one interpolating filter in parallel with the first stream of first digitized samples for generating at least a second stream of digitized samples at the first sampling rate but offset with respect to the first stream by a fraction of a sample time period.

Abstract: An active RC filter has an op-amp and a biasing circuit arranged to bias the op-amp to set a gain bandwidth product of the op-amp according to a desired pole frequency of the filter. The biasing circuit is operable according to an output of an RC calibration circuit. The op-amp can be an OTA transconductance amplifier, and the biasing circuit can be arranged to maintain a constant product of R and transconductance at an input of the transconductance amplifier. This biasing can help to set the pole frequency more accurately and can thus reduce the need for bandwidth margin to be provided to allow for manufacturing process variations.

Abstract: A receiver having circuitry for generating first digitized samples from a received analog signal at a first sampling rate, e.g. an ADC. An interpolating filter is used to generate second digitized samples which are estimates of samples obtainable by sampling the received analog signal at a second sample rate lower than the first sampling rate, second digitized samples being output at the first sampling rate and including at least one unusable sample. A circuit is provided for generating a signal for controlling components of the receive path downstream of the interpolation filter to prevent processing of the unusable second digitized samples.

Abstract: An equalizer for a multi carrier transmission system, converts a transmitted multi carrier signal into sampled frequency domain signals, and suppresses time domain delay dispersion, on the sampled frequency domain signals. It exploits circulant decomposition of a Toeplitz matrix to enable the computationally heavy evaluation of a matrix multiplied by a vector, to be avoided. Increased precision arises from the frequency domain processing being equivalent to a longer time domain FIR filter than is normally practical. The amount of compensation for different carriers can be adjusted, which can lead to increased precision.

Abstract: A memory system for use with a master-slave type bus such as an AHB bus has a memory, a bus interface to allow memory access from the bus, and a direct memory access interface to allow memory access from a DMA controller without occupying the bus. The system can reduce occupancy of the bus, it can allow dedicated DMA access protocols faster than the bus protocol to be used, and can remove or reduce the need for bus arbitration and associated circuitry and delays. An arbiter can arbitrate between the memory accesses and give priority to DMA accesses.

Abstract: An M-point Fractional Fourier is described using several 2M-points traditional Fourier transforms. The signal path is fed through a series of blocks including a first multiplier, a zero pad, an FFT, a second multiplier, an IFFT, a first half element, and a third multiplier. The first and third multipliers have as their other inputs a value exp(?j?n2?) for n=0:M?1, derived from the clock offset signal represented by ?.

Abstract: An up conversion mixer has a Gilbert cell arrangement including an input amplification part for producing an amplified signal coupled to a multiplication part, the multiplication part being arranged to multiply the amplified signal by a local oscillator signal and output a mixed signal, the mixer also having a capacitor coupled from a node between the input amplification part and the multiplication part, to a power supply line, for suppressing unwanted high frequency signal components of the output signal of the multiplication part. The linearity of such mixers can be improved considerably by this impedance on the source node of the switch transistors. This capacitance can be placed to either VSS or to VDD. Notably this improvement can be achieved with low power consumption since no additional power is needed for the increased performance.

Abstract: Wireless transceiver apparatus for operating in a part of the RF spectrum which is shared with a co-located second wireless transceiver apparatus. The first wireless transceiver apparatus includes, a wireless transceiver unit; an arbitration interface for interfacing with an arbitration entity which arbitrates access to the shared part of the RF spectrum between the first wireless transceiver apparatus and the second wireless transceiver apparatus; wherein the arbitration interface is adapted to signal time periods when the wireless transceiver unit is operational, or requests to be operational; and wherein the arbitration interface is adapted to signal data about and commands to the first wireless transceiver apparatus during other time periods. An enhanced arbitration entity is adapted to automatically detect and switch between two modes or interference reduction, e.g. a first interference reduction means such as AFH, a second interference reduction means such as PTA.

Abstract: A circuit for processing a packet based signal received over a Bluetooth radio link has a correlator to detect at least part of the access code. A correlator controller, reconfigures the correlator according to a timing of the access code, to detect at least part of the EDR synchronization sequence, and a demodulator demodulates the payload according to the detection. The correlator has an input signal register, a buffer for a sequence of at least part of the wanted signal values, and a series of comparators arranged to compare input signal values with corresponding ones of the wanted signal values at more than one offset. By such dual use of the same correlator, the receiver can be made more cost effective.

Abstract: A signal resampler carries out a time domain interpolation of an input signal for compensating for frequency offset, such as found in an ADSL system. A sample selector interpolator carries out part of the interpolation and a second, e.g. polynomial interpolator carries out the rest of the interpolation. The time interval between samples being interpolated, can be effectively divided between a sample selector interpolator and a small second, e.g. polynomial interpolator. The complexity of the second, e.g. polynomial interpolator can be reduced or its accuracy increased if it is effectively interpolating over a much smaller time interval. The sample selector interpolator can be an oversampling arrangement, and enable the order of the second, e.g. polynomial interpolator to be reduced. Selected ones of the oversampled samples are fed to the second, e.g. polynomial interpolator to keep the operating frequency lower. A chain of upsamplers can be used to generate the oversampled samples.

Abstract: First and second wireless transceiver units operate in the same portion of the RF spectrum. An arbitration device controls when the first and second wireless transceiver units can operate. An interface connects the first transceiver unit to the arbitration device and receives requests for operation. The interface permits the transceiver unit o use one of N possible priority levels for requests. The transceiver associates a transceiver priority level to a series of packets which is chosen from a range of M possible priority levels. The transceiver unit sends a sequence of requests to operate to the arbitration device, each request in the sequence having a priority level chosen from the range of N possible priority levels. The average value of the priority levels used in the sequence depends on the associated transceiver priority level.

Abstract: A clock offset compensation arrangement may include a fractional interpolator for applying a trigonometric interpolation to a sampled input signal according to a clock offset signal. It uses transform-based processing in the frequency domain. Compared to a polynomial type interpolation it may be easier to implement, and may achieve a closer approximation to an ideal interpolation. It may reduce the effects of non-linear type errors introduced by truncation of higher powers. The arrangement may be applied to receivers or transmitters of multi-carrier modems, as well as other applications which use rate adaptation or synchronization.

Abstract: A multicarrier transmission system uses a set of carriers spaced apart in frequency with a number of bits being assigned to each carrier. A transmitter has a mapper which maps a data signal to a parallel set of constellation values. A frequency domain-to-time domain transform stage converts the set of modulated carriers to a time-domain signal. A peak detector detects when the time-domain signal exceeds a predetermined criterion. A constellation modifier modifies the constellation value of at least one of the carriers to reduce the crest factor of the transmitted signal. A carrier is selected for modifying on the basis of a number of bits allocated to that carrier. The constellation modifier can select an alternative constellation value by an iterative method or by calculation. The constellation modifier can operate entirely in the time-domain.

Abstract: The present invention discloses a system and a methodology for enhancing performance during wireless communications by reducing system latency, MIPS requirements and power consumption. The present invention discloses a system and method of wireless data communication in which part of upper layer stack processing is performed on a controller to relieve a host processor of some data intensive operations. After the initial connection establishment phase in which the controller retrieves certain information required for data transmission and stores the same locally, the data source provides data directly to the controller without routing the data through the host. The host is relieved of the data processing that needs to be done while the data is being transferred. Hence, the overall latency of the system is improved because of the optimal routing of data traffic.

Abstract: A radio transmission method and a radio transmitter device for radio transmission of an audio signal from an audio device to a radio receiver wherein an audio signal is received from the audio device, and an RF signal is transmitted simultaneously which is modulated with the audio signal on each of a set of at least two different RF channels. Within each of the transmitted RF signals, information identifying at least the other RF channels in the set of RF channels is included.