Abstract: A device has a radio transmitter for a first radio link such as a Bluetooth link, having a coexistence controller arranged to communicate with a co-located other radio transmitter for another radio link, to enable both radio links to use potentially conflicting transmission frequencies. A link monitor monitors the first radio link, according to an output from the coexistence controller. By making the link monitor dependent on the coexistence controller, it can distinguish between transmission losses caused by the coexistence interface, and those caused by other effects, to reduce the risk of a data rate controller unnecessarily reducing a transmission rate if transmission losses caused by the coexistence control are misinterpreted as a drop in link quality.

Abstract: A buffer circuit buffers incoming signals, from a local oscillator generator to a mixing circuit and has a push-pull circuit having two inputs, a first being coupled to a first incoming signal, and a second of the inputs being coupled to one of the buffered versions of the incoming signals, having a phase related to that of the first incoming signal. By coupling a second input to a buffered version rather than to the incoming signal, the load presented to the preceding circuit can be halved, while maintaining reduced power consumption. By using as a second input, a signal which is phase related to the first incoming signal, the normal operation of the push-pull circuit can be maintained. The incoming signals from the LO generator can be differential IQ signals and the buffered version of the further incoming signal be in phase with the first incoming signal.

Abstract: An active RC filter has an op-amp and a biasing circuit arranged to bias the op-amp to set a gain bandwidth product of the op-amp according to a desired pole frequency of the filter. The biasing circuit is operable according to an output of an RC calibration circuit. The op-amp can be an OTA transconductance amplifier, and the biasing circuit can be arranged to maintain a constant product of R and transconductance at an input of the transconductance amplifier. This biasing can help to set the pole frequency more accurately and can thus reduce the need for bandwidth margin to be provided to allow for manufacturing process variations.

Abstract: A Phase-Locked Loop with multiphase clocks is provided. The Phase-Locked Loop includes a main loop, a calibration loop, and a Demultiplexer. The main loop includes, coupled in series, a Phase Frequency Detector, a Main Charge Pump, a Main Loop Filter, a Multi-Phase Voltage Controlled Oscillator and a Phase-switching Fractional Divider. The calibration loop includes Y Calibration Loop Filters, with Y being an integer, coupled to the Multi-Phase Voltage Controlled Oscillator, and Control Logic for controlling the Phase-Switching Fractional Divider. The Demultiplexer is coupled between an output of the Main Charge Pump and inputs of the Main Loop Filter and the Y Calibration Loop Filters. A Reference Frequency Signal is coupled to the Phase Frequency Detector, a control signal from the Control Logic is coupled to the Demultiplexer, and a Calibration Signal is coupled to a control input of the Control Logic.

Abstract: A Phase-Locked Loop with multiphase clocks is provided. The Phase-Locked Loop includes a main loop, a calibration loop, and Control Logic. The main loop includes, coupled in series, a Phase Frequency Detector, a Main Charge Pump, a Main Loop Filter, a Multi-Phase Voltage Controlled Oscillator and a Phase-switching Fractional Divider. The calibration loop is coupled to the Phase Frequency Detector, and comprises a Calibration Charge Pump, a Demultiplexer and Y Calibration Loop Filters, with Y being an integer. The Control Logic controls the Phase-Switching Fractional Divider and the Demultiplexer. A Reference Frequency Signal is coupled to the Phase Frequency Detector and a Calibration Signal is coupled to the calibration loop. The main loop further comprises a Phase-adjusting Block coupled to a Multiplexer. The Phase-adjusting Block is arranged so as to receive at least one correction signal from the calibration loop.

Abstract: A serial in random out memory circuit has a number of memory cells integrated with write control circuitry for writing a sequence of data inputs to sequential locations in the memory cells. Read control circuitry is integrated to receive address signals from an external device and provide a random access read output from the memory cells, mapped into an address range of the external device. Compared to circuits using discrete components and conventional RAM chips, the integrated SIRO can enable some of the circuitry or external software to be dispensed with and so reduce costs or increase performance. The memory cells can be arranged in a number of blocks, selectable one at a time for mapping to the external device address range.

Abstract: A receiver is described including circuitry for deriving at least a first stream of first digitized samples from a received analog signal at a first sampling rate, circuitry for selecting a first sampling point and at least a second sampling point, a demodulator for demodulating first and second symbols from the at least first stream of samples based on the first and the at least second sampling points, and circuitry for determining a value related to a demodulation accuracy for the first and second symbols and for outputting a signal, the circuitry for selecting being adapted to alter the sampling point based on the signal. By assessing a demodulation accuracy in real time clock drift can be compensated. The demodulation accuracy can be a value related to a phase error or an error energy such as EVM or DEVM for each demodulated symbol.

Abstract: A receive path in a receiver including circuitry for deriving a first stream of first digitized samples from a received analog signal at a first sampling rate, and at least one interpolating filter in parallel with the first stream of first digitized samples for generating at least a second stream of digitized samples at the first sampling rate but offset with respect to the first stream by a fraction of a sample time period.

Abstract: A receiver having circuitry for generating first digitized samples from a received analog signal at a first sampling rate, e.g. an ADC. An interpolating filter is used to generate second digitized samples which are estimates of samples obtainable by sampling the received analog signal at a second sample rate lower than the first sampling rate, second digitized samples being output at the first sampling rate and including at least one unusable sample. A circuit is provided for generating a signal for controlling components of the receive path downstream of the interpolation filter to prevent processing of the unusable second digitized samples.

Abstract: Method and apparatus for a wireless receiver are described which derive at least a first stream of first digitized samples from a received analog signal at a first sampling rate and identify a first frequency offset based on a plurality of parallel correlations using complex reference signals which differ from each other by phase offsets. A second frequency offset is identified based on tracking a demodulation accuracy for each symbol which is demodulated from the first stream of digitized samples. These frequency offsets can be used to rotate decision areas in the demodulator. The methods and apparatus may be used in a Bluetooth receiver.

Abstract: A method and circuit are provided for controlling access of two synchronous busses with asynchronous clocks to a synchronous single port Random Access Memory (RAM). In one preferred method, the clock of bus A is switched off via a control flip-flop and then the clock of bus B is switched on, allowing the control and data signals to pass through simple multiplexers. Bus B becomes the owner of the RAM. Later, the clock of bus B is switched off via the control flip-flop and then clock of bus A is switched on, such that bus A becomes owner of the bus. This allows any relative speed between the bus clocks.

Abstract: A memory system for use with a master-slave type bus such as an AHB bus has a memory, a bus interface to allow memory access from the bus, and a direct memory access interface to allow memory access from a DMA controller without occupying the bus. The system can reduce occupancy of the bus, it can allow dedicated DMA access protocols faster than the bus protocol to be used, and can remove or reduce the need for bus arbitration and associated circuitry and delays. An arbiter can arbitrate between the memory accesses and give priority to DMA accesses.

Abstract: An RF transmitter suitable for Bluetooth transmissions has an IF modulator and an RF modulator, the IF modulator being arranged to use a very-low-IF-frequency, smaller than half the channel bandwidth, such that spurious unwanted modulation components fall in other channels having a channel number within one or two of a channel being transmitted. This can reduce the VCO pulling problem and reduce adjacent channel power degradation compared to using higher IF frequencies. The local oscillator PLL's fractionality is used in order to optimize the adjacent power frequency plan by selecting the most appropriate IF frequency. For the Bluetooth application, the IF frequency is <500 kHz, and the main non-filtered spurious components (1LO·xBB with x: ?3, ?2, . . . , +3) image, carrier, pulling, for both 0 and 1 FM signals, are positioned in frequency bands of adjacent channels.

Abstract: A line driver circuit couples a data transceiver to a line. The line driver includes a differential amplifier which receives a signal for transmission on the line. First and second feedback paths connect between outputs of the amplifier and inputs of the amplifier. A bridge couples the differential amplifier to the line. The bridge comprises two matching impedance and two secondary transformer winding. Each matching impedance is connected in series with a secondary transformer winding between the outputs of the amplifiers. Two feedback branches connect between internal nodes of the secondary windings and the inputs of the differential amplifier. The line driver circuit is less sensitive to accuracy of component values while providing an increased dynamic on the line for a given dynamic of the transceiver and a given attenuation of the received signal.

Abstract: First and second wireless transceiver units operate in the same portion of the RF spectrum. An arbitration device controls when the first and second wireless transceiver units can operate. An interface connects the first transceiver unit to the arbitration device and receives requests for operation. The interface permits the transceiver unit o use one of N possible priority levels for requests. The transceiver associates a transceiver priority level to a series of packets which is chosen from a range of M possible priority levels. The transceiver unit sends a sequence of requests to operate to the arbitration device, each request in the sequence having a priority level chosen from the range of N possible priority levels. The average value of the priority levels used in the sequence depends on the associated transceiver priority level.

Abstract: A Phase-Locked Loop is provided that includes a main loop, a calibration loop, and Control Logic. The main loop comprises, coupled in series, a Phase Frequency Detector, a Main Charge Pump, a Main Loop Filter, a Voltage Controlled Oscillator and a Frequency Divider. The calibration loop is coupled to the Phase Frequency Detector and comprises a Calibration Charge Pump and a Calibration Loop Filter. The Control Logic controls the Frequency Divider and receives a control input signal. A Reference Frequency Signal is coupled to the Phase Frequency Detector and the Control Logic, and a calibration signal is coupled to the calibration loop. Additionally, the main loop further comprises a delay generator controlled by the Control Logic and arranged to receive correction signals from the calibration loop and to send an output signal to the Phase Frequency Detector.

Abstract: A Bluetooth master radio frequency unit addresses a slave radio frequency unit, to enable the slave to synchronize to the master, by sending poll packets and optionally null packets over an active link, the master being arranged so that receipt of a response from the slave unit to a poll packet is sufficient to maintain the active link. The slave unit does not have to respond to all of the poll packets. This approach can allow the slave to preserve more (transmit) power by going into a deep sleep mode in which a low power oscillator may be used while still allowing the master unit to detect whether the slave has resynchronized or not (and thus to update a Link Supervision Timer, for example).

Abstract: A low noise differential amplifier has a pair of single ended common-gate or common-base circuits and cross coupling of an input of one of the pair to the gate or base of the other one of the pair. This cross-coupling puts the differential input voltage over the Gate-Source of the common-gate transistor (or Base-Emitter of the common base transistor). This means that the same input impedance and gain can be made with half the current compared to a basic common-gate topology. The cross-coupling means the noise generated by the positive side of the common-gate structure ends up partly on the negative output and vice versa, and so the Noise Figure can be less than 3 dB.

Abstract: A method and circuit are provided for controlling access of two synchronous busses with asynchronous clocks to a synchronous single port Random Access Memory (RAM). In one preferred method, the clock of bus A is switched off via a control flip-flop and then the clock of bus B is switched on, allowing the control and data signals to pass through simple multiplexers. Bus B becomes the owner of the RAM. Later, the clock of bus B is switched off via the control flip-flop and then clock of bus A is switched on, such that bus A becomes owner of the bus. This allows any relative speed between the bus clocks.

Abstract: An M-point Fractional Fourier is described using several 2M-points traditional Fourier transforms. The signal path is fed through a series of blocks including a first multiplier, a zero pad, an FFT, a second multiplier, an IFFT, a first half element, and a third multiplier. The first and third multipliers have as their other inputs a value exp(−jnn2&agr;) for n=0:M−1, derived from the clock offset signal represented by &agr;.