Patents Assigned to STMicroelectronics (Crolles 2)
  • Integrated circuit comprising a junction field effect transistor
    Patent number: 11342449
    Abstract: An integrated circuit includes a junction field-effect transistor formed in a semiconductor substrate. The junction field-effect transistor includes a drain region, a source region, a channel region, and a gate region. A first isolating region separates the drain region from both the gate region and the channel region. A first connection region connects the drain region to the channel region by passing underneath the first isolating region in the semiconductor substrate. A second isolating region separates the source region from both the gate region and the channel region. A second connection region connects the source region to the channel region by passing underneath the second isolating region in the semiconductor substrate.
    Type: Grant
    Filed: November 11, 2020
    Date of Patent: May 24, 2022
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventor: Jean Jimenez Martinez
  • Quenching of a SPAD
    Patent number: 11336853
    Abstract: The present disclosure relates to a device that includes a photodiode having a first terminal that is coupled by a resistor to a first rail configured to receive a high supply potential and a second terminal that is coupled by a switch to a second rail configured to receive a reference potential. A read circuit is configured to provide a pulse when the photodiode enters into avalanche, and a control circuit is configured to control an opening of the switch in response to a beginning of the pulse and to control a closing of the switch in response to an end of the pulse.
    Type: Grant
    Filed: October 5, 2020
    Date of Patent: May 17, 2022
    Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics (Research & Development) Limited
    Inventors: Raul Andres Bianchi, Matteo Maria Vignetti, Bruce Rae
  • DEVICE COMPRISING A TRANSISTOR
    Publication number: 20220149151
    Abstract: A device including a transistor is fabricated by forming a first part of a first region of the transistor through the implantation of dopants through a first opening. The second region of the transistor is then formed in the first opening by epitaxy.
    Type: Application
    Filed: January 26, 2022
    Publication date: May 12, 2022
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Alexis GAUTHIER, Pascal CHEVALIER, Gregory AVENIER
  • Electro-optical modulator and methods of formation thereof
    Patent number: 11327346
    Abstract: In one embodiment, an electro-optical modulator includes a waveguide having a first major surface and a second major surface opposite the first major surface. A cavity is disposed in the waveguide. Multiple quantum wells are disposed in the cavity.
    Type: Grant
    Filed: August 13, 2019
    Date of Patent: May 10, 2022
    Assignee: STMICROELECTRONICS (CROLLES 2) SAS
    Inventor: Charles Baudot
  • Germanium-on-silicon laser in CMOS technology
    Patent number: 11329455
    Abstract: A germanium waveguide is formed from a P-type silicon substrate that is coated with a heavily-doped N-type germanium layer and a first N-type doped silicon layer. Trenches are etched into the silicon substrate to form a stack of a substrate strip, a germanium strip, and a first silicon strip. This structure is then coated with a silicon nitride layer.
    Type: Grant
    Filed: May 6, 2020
    Date of Patent: May 10, 2022
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Mathias Prost, Moustafa El Kurdi, Philippe Boucaud, Frederic Boeuf
  • Co-integration of bulk and SOI transistors
    Patent number: 11329067
    Abstract: An electronic integrated circuit chip includes a first transistor arranged inside and on top of a solid substrate, a second transistor arranged inside and on top of a layer of semiconductor material on insulator having a first thickness, and a third transistor arranged inside and on top of a layer of semiconductor material on insulator having a second thickness. The second thickness is greater than the first thickness. The solid substrate extends underneath the layers of semiconductor material and is insulated from those layers by the insulator.
    Type: Grant
    Filed: June 11, 2020
    Date of Patent: May 10, 2022
    Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics (Rousset) SAS
    Inventors: Jean-Jacques Fagot, Philippe Boivin, Franck Arnaud
  • Memory cell comprising a phase-change material
    Patent number: 11329225
    Abstract: A memory cell includes a heating element topped with a phase-change material. Two first silicon oxide regions laterally surround the heating element along a first direction. Two second silicon oxide regions laterally surround the heating element along a second direction orthogonal to the first direction. Top surfaces of the heating element and the two first silicon oxide regions are coplanar such that the heating element and the two first silicon oxide regions have a same thickness.
    Type: Grant
    Filed: September 4, 2020
    Date of Patent: May 10, 2022
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventor: Olivier Hinsinger
  • PHASE-CHANGE MEMORY
    Publication number: 20220140232
    Abstract: The present description concerns a device including phase-change memory cells, each memory cell including a first resistive element in lateral contact with a second element made of a phase-change material.
    Type: Application
    Filed: October 21, 2021
    Publication date: May 5, 2022
    Applicants: STMicroelectronics (Crolles 2) SAS, STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Philippe BOIVIN, Roberto SIMOLA, Yohann MOUSTAPHA-RABAULT
  • Contacts for electronic component
    Patent number: 11322363
    Abstract: Atoms are implanted in a semiconductor region at a higher concentration in a peripheral part of the semiconductor region than in a central part of the semiconductor region. A metallic region is then formed to cover the semiconductor region. A heat treatment is the performed to form an intermetallic region from the metallic region and the semiconductor region.
    Type: Grant
    Filed: June 4, 2020
    Date of Patent: May 3, 2022
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Julien Borrel, Magali Gregoire
  • METHOD FOR PRODUCING A DIODE
    Publication number: 20220130728
    Abstract: At least one bipolar transistor and at least one variable capacitance diode are jointly produced by a method on a common substrate.
    Type: Application
    Filed: January 4, 2022
    Publication date: April 28, 2022
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Pascal CHEVALIER, Alexis GAUTHIER, Gregory AVENIER
  • SEMICONDUCTOR INTEGRATED CIRCUIT COMPONENT
    Publication number: 20220131005
    Abstract: An integrated circuit includes a semiconductor substrate having a first type of conductivity and a semiconductor component. The semiconductor component includes: a buried semiconductor region having a second type of conductivity opposite to the first type of conductivity; a first gate region and a second gate region each extending in depth from a front face of the semiconductor substrate to the buried semiconductor region; a third gate region extending in depth from the front face of the semiconductor substrate and being electrically connected to the buried semiconductor region; and an active area delimited by the first gate region, the second gate region and the buried semiconductor region.
    Type: Application
    Filed: October 19, 2021
    Publication date: April 28, 2022
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Benoit FROMENT, Thomas CABOUT
  • BIPOLAR TRANSISTOR AND MANUFACTURING METHOD
    Publication number: 20220122969
    Abstract: A bipolar transistor includes a collector region having a first doped portion located in a substrate and a second doped portion covering and in contact with an area of the first doped portion. The collector region has a doping profile having a peak in the first portion and a decrease from this peak up to in the second portion.
    Type: Application
    Filed: October 18, 2021
    Publication date: April 21, 2022
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Edoardo BREZZA, Alexis GAUTHIER
  • SPAD PIXEL
    Publication number: 20220115419
    Abstract: An electronic device includes a stack of a first level having a SPAD, a second level having a quench circuit for said SPAD, and a third level having a circuit for processing data generated by said SPAD. A method for making the device includes: a) forming of the first level; b) bonding, on the first level, by molecular bonding, of a stack of layers including a semiconductor layer; and c) forming the quench circuit of the second level in the semiconductor layer.
    Type: Application
    Filed: October 11, 2021
    Publication date: April 14, 2022
    Applicants: STMicroelectronics (Crolles 2) SAS, STMicroelectronics (Research & Development) Limited
    Inventors: Francois GUYADER, Sara PELLEGRINI, Bruce RAE
  • Bipolar transistor
    Patent number: 11296205
    Abstract: A bipolar transistor includes a collector. The collector is formed by: a first portion of the collector which extends under an insulating trench, and a second portion of the collector which crosses through the insulating trench. The first and second portions of the collector are in physical contact.
    Type: Grant
    Filed: October 2, 2019
    Date of Patent: April 5, 2022
    Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics SA
    Inventors: Alexis Gauthier, Pascal Chevalier
  • INTEGRATED PHOTONIC DEVICE WITH IMPROVED OPTICAL COUPLING
    Publication number: 20220091330
    Abstract: A three-dimensional photonic integrated structure includes a first semiconductor substrate and a second semiconductor substrate. The first substrate incorporates a first waveguide and the second semiconductor substrate incorporates a second waveguide. An intermediate region located between the two substrates is formed by a one dielectric layer. The second substrate further includes an optical coupler configured for receiving a light signal. The first substrate and dielectric layer form a reflective element located below and opposite the grating coupler in order to reflect at least one part of the light signal.
    Type: Application
    Filed: December 2, 2021
    Publication date: March 24, 2022
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Frederic BOEUF, Charles BAUDOT
  • OPTICAL FILTER AND CORRESPONDING MANUFACTURING METHOD
    Publication number: 20220082743
    Abstract: An optical filter includes a carrier layer made of a first material. A periodic grating of posts is disposed on the carrier layer in a periodic pattern configured by characteristic dimensions. The posts are made of a second material. A layer made of a third material encompasses the periodic grating of posts and covers the carrier layer. The third material has a refractive index that is different from a refractive index of the second material. Characteristic dimensions of the periodic grating of posts are smaller than an interfering wavelength and are configured to selectively reflect light at the interfering wavelength on the periodic grating of posts.
    Type: Application
    Filed: September 8, 2021
    Publication date: March 17, 2022
    Applicants: STMicroelectronics SA, STMicroelectronics (Crolles 2) SAS
    Inventors: Olivier LE NEEL, Stephane ZOLL, Stephane MONFRAY
  • PIXEL WITH AN IMPROVED QUANTUM EFFICIENCY
    Publication number: 20220085084
    Abstract: The present disclosure relates to a pixel comprising: a photodiode comprising a portion of a substrate of a semiconductor material, extending vertically from a first face of the substrate to a second face of the substrate configured to receive light; a layer of a first material covering each of the lateral surfaces of the portion; a layer of a second material covering the portion on the side of the first face, first and second material having refractive indexes lower than that of the semiconductor material; and a diffractive structure disposed on a face of the photodiode on the side of the second face.
    Type: Application
    Filed: September 9, 2021
    Publication date: March 17, 2022
    Applicants: STMICROELECTRONICS (RESEARCH & DEVELOPMENT) LIMITED, STMicroelectronics (Crolles 2) SAS
    Inventors: Raul Andres BIANCHI, Marios BARLAS, Alexandre LOPEZ, Bastien MAMDY, Bruce RAE, Isobel NICHOLSON
  • ELECTRONIC DEVICE COMPRISING A PHOTOSENSITIVE SEMICONDUCTOR REGION AND CORRESPONDING MANUFACTURING METHOD
    Publication number: 20220085082
    Abstract: A photosensitive semiconductor region is configured to be illuminated through a rear face. A periodic array of pads formed of a first material is provided at the front face. The periodic array has an outline with a periodic pattern parameterized by characteristic dimensions. The outline forms an interface between the first material and a second material, where the first and second materials have different optical indices. The characteristic dimensions of the periodic pattern are less than a wavelength of interest and are configured to produce at the interface a reflection of light at the wavelength of interest towards the photosensitive semiconductor region.
    Type: Application
    Filed: September 8, 2021
    Publication date: March 17, 2022
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Axel CROCHERIE, Stephane MONFRAY
  • Method for forming a device comprising a bipolar transistor
    Patent number: 11276752
    Abstract: A device including a transistor is fabricated by forming a first part of a first region of the transistor through the implantation of dopants through a first opening. The second region of the transistor is then formed in the first opening by epitaxy.
    Type: Grant
    Filed: August 17, 2020
    Date of Patent: March 15, 2022
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Alexis Gauthier, Pascal Chevalier, Gregory Avenier
  • Photonic IC chip
    Patent number: 11269141
    Abstract: A photonic integrated circuit chip includes vertical grating couplers defined in a first layer. Second insulating layers overlie the vertical grating coupler and an interconnection structure with metal levels is embedded in the second insulating layers. A cavity extends in depth through the second insulating layers all the way to an intermediate level between the couplers and the metal level closest to the couplers. The cavity has lateral dimensions such that the cavity is capable of receiving a block for holding an array of optical fibers intended to be optically coupled to the couplers.
    Type: Grant
    Filed: March 17, 2020
    Date of Patent: March 8, 2022
    Assignees: STMICROELECTRONICS S.R.L., STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: Frédéric Boeuf, Luca Maggi