Patents Assigned to STMicroelectronics (Crolles 2)
  • ELECTRONIC SECURITY COMPONENT
    Publication number: 20210399094
    Abstract: An electronic component is formed on and in a semiconductor substrate. The component includes source and drain regions and a gate region between the source and drain regions. Two dielectric lateral spacing regions are provided on the semiconductor substrate against sides of the gate region. An electrical connection, formed by a silicide on a surface of at least one of said dielectric lateral spacing region, is configured to electrically connect the gate region to at least one of the source region and the drain region.
    Type: Application
    Filed: June 21, 2021
    Publication date: December 23, 2021
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventor: Benoit FROMENT
  • Integrated electro-optical device
    Patent number: 11199731
    Abstract: A device, includes: a ring waveguide; a diode comprising a junction extending at least partly in the ring waveguide; and a first circuit configured to supply a signal representative of a leakage current in the diode.
    Type: Grant
    Filed: October 6, 2020
    Date of Patent: December 14, 2021
    Assignees: STMICROELECTRONICS (CROLLES 2) SAS, COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Patrick Le Maitre, Nicolas Michit, Jean-Francois Carpentier, Benoit Charbonnier
  • IONIZING RADIATION DETECTOR
    Publication number: 20210382189
    Abstract: A diode and a transistor are connected in parallel. The transistor is located on a first doped region forming a PN junction of the diode with a second doped region located under the first region. The circuit functions as an ionizing radiation detection cell by generating a current through the PN junction which changes by a voltage generated across the transistor. This change in voltage is compared to a threshold to detect the ionizing radiation.
    Type: Application
    Filed: August 23, 2021
    Publication date: December 9, 2021
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Gilles GASIOT, Fady ABOUZEID
  • Low-noise wide dynamic range image sensor
    Patent number: 11195872
    Abstract: A semiconductor image sensor includes a plurality of pixels. Each pixel of the sensor includes a semiconductor substrate having opposite front and back sides and laterally delimited by a first insulating wall including a first conductive core insulated from the substrate, electron-hole pairs being capable of forming in the substrate due to a back-side illumination. A circuit is configured to maintain, during a first phase in a first operating mode, the first conductive core at a first potential and to maintain, during at least a portion of the first phase in a second operating mode, the first conductive core at a second potential different from the first potential.
    Type: Grant
    Filed: August 21, 2019
    Date of Patent: December 7, 2021
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Francois Roy, Stephane Hulot, Andrej Suler, Nicolas Virollet
  • INTEGRATED OPTICAL SENSOR WITH PINNED PHOTODIODES
    Publication number: 20210376170
    Abstract: An integrated optical sensor is formed by a pinned photodiode. A semiconductor substrate includes a first semiconductor region having a first type of conductivity located between a second semiconductor region having a second type of conductivity opposite to the first type one and a third semiconductor region having the second type of conductivity. The third semiconductor region is thicker, less doped and located deeper in the substrate than the second semiconductor region. The third semiconductor region includes both silicon and germanium. In one implementation, the germanium within the third semiconductor region has at least one concentration gradient. In another implementation, the germanium concentration within the third semiconductor region is substantially constant.
    Type: Application
    Filed: May 19, 2021
    Publication date: December 2, 2021
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventor: Didier DUTARTRE
  • INTEGRATED PHYSICAL UNCLONABLE FUNCTION DEVICE
    Publication number: 20210377058
    Abstract: An integrated physical unclonable function device includes at least one reference capacitor and a number of comparison capacitors. A capacitance determination circuit operates to determine a capacitance of the at least one reference capacitor and a capacitance of each comparison capacitor. The determined capacitances of the comparison capacitors are then compared to the determined capacitance of the reference capacitor by a comparison circuit. A digital word is then generated with bit values indicative of a result of the comparisons made by the comparison circuit.
    Type: Application
    Filed: May 25, 2021
    Publication date: December 2, 2021
    Applicants: STMicroelectronics (Crolles 2) SAS, STMicroelectronics (Rousset) SAS
    Inventors: Benoit Froment, Jean-Marc Voisin
  • Opto electrical test measurement system for integrated photonic devices and circuits
    Patent number: 11187613
    Abstract: An optical testing circuit on a wafer includes an optical input configured to receive an optical test signal and photodetectors configured to generate corresponding electrical signals in response to optical processing of the optical test signal through the optical testing circuit. The electrical signals are simultaneously sensed by a probe circuit and then processed. In one process, test data from the electrical signals is simultaneously generated at each step of a sweep in wavelength of the optical test signal and output in response to a step change. In another process, the electrical signals are sequentially selected and the sweep in wavelength of the optical test signal is performed for each selected electrical signal to generate the test data.
    Type: Grant
    Filed: April 30, 2020
    Date of Patent: November 30, 2021
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Philippe Grosse, Patrick Le Maitre, Jean-Francois Carpentier
  • Chip protected against back-face attacks
    Patent number: 11183468
    Abstract: A semiconductor chip includes at least two insulated vias passing through the chip from the front face to the rear face in which, on the side of the rear face, the vias are connected to one and the same conducting strip and, on the side of the front face, each via is separated from a conducting pad by a layer of a dielectric.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: November 23, 2021
    Assignee: STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: Sebastien Petitdidier, Nicolas Hotellier, Raul Andres Bianchi, Alexis Farcy, Benoît Froment
  • Filtering device in a waveguide
    Patent number: 11169325
    Abstract: An optical waveguide is configured to propagate a light signal. Metal vias are arranged along and on either side of a portion of the optical waveguide. Additional metal vias are further arranged along and on either side of the optical waveguide both upstream and downstream of the portion of the optical waveguide. The metal vias and additional metal vias are oriented orthogonal to a same plane, the same plane being orthogonal to a transverse cross-section of the portion of the optical waveguide.
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: November 9, 2021
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Sylvain Guerber, Charles Baudot
  • Manufacturing of cavities
    Patent number: 11171034
    Abstract: A substrate includes a first solid semiconductor region and a second semiconductor on insulator region. First and second cavities are simultaneously formed in the first and second regions, respectively, of the substrate using etching processes in two steps which form an upper portion and a lower portion of each cavity. The first and second cavities will each have a step at a level of an upper surface of the insulator of the second semiconductor on insulator region. A further oxidation of the first cavity produces a rounded or cut-off area for the upper portion.
    Type: Grant
    Filed: December 9, 2019
    Date of Patent: November 9, 2021
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Pascal Gouraud, Delia Ristoiu
  • PIXEL COMPRISING A CHARGE STORAGE ZONE
    Publication number: 20210343766
    Abstract: A pixel includes a photoconversion zone, an insulated vertical electrode and at least one charge storage zone. The photoconversion zone belongs to a first part of a semiconductor substrate and each charge storage zone belongs to a second part of the substrate physically separated from the first part of the substrate by the insulated vertical electrode.
    Type: Application
    Filed: April 8, 2021
    Publication date: November 4, 2021
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Boris RODRIGUES GONCALVES, Frederic LALANNE
  • STRAINED TRANSISTORS AND PHASE CHANGE MEMORY
    Publication number: 20210343788
    Abstract: A method for manufacturing an electronic chip includes providing a semiconductor layer located on an insulator covering a semiconductor substrate. First and second portions of the semiconductor layer are oxidized up to the insulator. Stresses are generated in third portions of the semiconductor layer, and each of the third portions extend between two portions of the semiconductor layer that are oxidized. Cavities are formed which extend at least to the substrate through the second portions and the insulator. Bipolar transistors are formed in at least part of the cavities and first field effect transistors are formed in and on the third portions. Phase change memory points are coupled to the bipolar transistors.
    Type: Application
    Filed: April 29, 2021
    Publication date: November 4, 2021
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Remy BERTHELON, Olivier WEBER
  • PIXEL WITH GLOBAL SHUTTER
    Publication number: 20210344866
    Abstract: A pixel includes a photosensitive circuit, a sense node, a first transistor and a first capacitor. A first electrode of the first capacitor is connected to a control terminal of the first transistor. A second electrode of the first capacitor is to a node of application of a first control signal.
    Type: Application
    Filed: July 12, 2021
    Publication date: November 4, 2021
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Frederic LALANNE, Pierre MALINGE
  • Structure comprising a strained semiconductor layer on a heat sink
    Patent number: 11165220
    Abstract: A structure includes a semiconductor support, a semiconductor region overlying the semiconductor support, a silicon nitride layer surrounding and straining the semiconductor region, and a metal foot separating the silicon nitride layer from the semiconductor support. The semiconductor region includes germanium. The semiconductor region can be a resonator of a laser or a waveguide.
    Type: Grant
    Filed: October 19, 2017
    Date of Patent: November 2, 2021
    Assignees: STMicroelectronics (Crolles 2) SAS, Universite Paris-Saclay, Centre National de la Recherche Scientifique
    Inventors: Anas Elbaz, Moustafa El Kurdi, Abdelhanin Aassime, Philippe Boucaud, Frederic Boeuf
  • IMAGE ACQUISITION DEVICE
    Publication number: 20210327936
    Abstract: An image acquisition device includes an array of color filters and an array of microlenses over the array of color filters. At least one layer made from an inorganic dielectric material is formed between the array of color filters and the array of microlenses.
    Type: Application
    Filed: April 7, 2021
    Publication date: October 21, 2021
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Mickael FOUREL, Laurent-Luc CHAPELON
  • INTEGRATED CIRCUIT COMPRISING A SUBSTRATE EQUIPPED WITH A TRAP-RICH REGION, AND FABRICATING PROCESS
    Publication number: 20210327834
    Abstract: An integrated circuit includes a substrate having at least one first domain and at least one second domain that is different from the at least one first domain. A trap-rich region is provided in the substrate at the locations of the at least one second domain only. Locations of the at least one first domain do not include the trap-rich region.
    Type: Application
    Filed: June 28, 2021
    Publication date: October 21, 2021
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventor: Didier DUTARTRE
  • Integrated circuit including bipolar transistors
    Patent number: 11152430
    Abstract: The disclosure relates to integrated circuits and methods including one or more rows of transistors. In an embodiment, an integrated circuit includes a row of bipolar transistors including a plurality of first conduction regions, a second conduction region, and a common base between the first conduction regions and the second conduction region. An insulating trench is in contact with each bipolar transistor of the row of bipolar transistors. A conductive layer is on the insulating trench and the common base between the first conduction regions. A spacer layer is between the conductive layer and the first conduction regions.
    Type: Grant
    Filed: April 4, 2019
    Date of Patent: October 19, 2021
    Assignees: STMicroelectronics (Rousset) SAS, STMicroelectronics (Crolles 2) SAS
    Inventors: Philippe Boivin, Jean Jacques Fagot, Emmanuel Petitprez, Emeline Souchier, Olivier Weber
  • Electronic component manufacturing method
    Patent number: 11152570
    Abstract: The disclosure concerns an electronic component manufacturing method including a first step of etching at least one first layer followed, with no exposure to oxygen, by a second step of passivating the first layer.
    Type: Grant
    Filed: September 20, 2019
    Date of Patent: October 19, 2021
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Yann Canvel, Sebastien Lagrasta, Sebastien Barnola, Christelle Boixaderas
  • Capacitive optical modulator
    Patent number: 11150533
    Abstract: A capacitive electro-optical modulator includes a silicon layer, a germanium or silicon-germanium strip overlying the silicon layer, and a silicon strip overlying the germanium or silicon-germanium strip. The silicon strip is wider than the germanium or silicon-germanium strip. An insulator is laterally adjacent the germanium or silicon-germanium strip and the silicon strip and has an upper surface that is flush with an upper surface of the silicon strip. An insulating layer overlies the insulator and the silicon strip. A layer of III-V material overlies the insulating layer. The layer of III-V material is formed as a third strip arranged facing the silicon strip and separated therefrom by a portion of the insulating layer.
    Type: Grant
    Filed: July 16, 2020
    Date of Patent: October 19, 2021
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Frédéric Boeuf, Cyrille Barrera
  • Optical diffuser and its method of manufacture
    Patent number: 11150388
    Abstract: Methods of manufacture of an optical diffuser. In one embodiment, an optical diffuser is formed by providing a wafer including a silicon slice of which an upper face is covered with a first layer made of a first material itself covered with a second layer made of a second selectively etchable material with respect to the first material. The method further includes forming openings in the second layer extending up to the first layer and filling the openings in the second layer with a third material. The method yet further includes bonding a glass substrate to the wafer on the side of its upper face and removing the silicon slice.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: October 19, 2021
    Assignee: STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: Vincent Farys, Alain Inard, Olivier Noblanc