Abstract: A process for manufacturing a silicon carbide semiconductor device includes providing a silicon carbide wafer, having a substrate. An epitaxial growth for formation of an epitaxial layer, having a top surface, is carried out on the substrate. Following upon the step of carrying out an epitaxial growth, the process includes the step of removing a surface portion of the epitaxial layer starting from the top surface so as to remove surface damages present at the top surface as a result of propagation of dislocations from the substrate during the previous epitaxial growth and so as to define a resulting top surface substantially free of defects.

Abstract: A semiconductor substrate includes excavations which form trenches sunk. A capacitive element includes: a first dielectric envelope conforming to sides and bottoms of the trenches; a first semiconductor layer conforming to a surface of the first dielectric envelope in the trenches; a second dielectric envelope conforming to a surface of the first semiconductor layer in the trenches; and a second semiconductor layer conforming to a surface of the second dielectric envelope in the trenches.

Abstract: The present disclosure is directed to a semiconductor die with multiple contact pads electrically coupled to a single lead via a single wire, and methods for fabricating the same. In one or more embodiments, multiple contact pads are electrically coupled to each other by a plurality of conductive layers stacked on top of each other. The uppermost conductive layer is then electrically coupled to a single lead via a single wire.

Abstract: An optoelectronic device includes a photodiode. At least a portion of an active area of the photodiode is separated from a neighboring photodiode by a first wall including a conductive core and an insulating sheath and by a second optical insulation wall. The first wall and second optical insulation wall further extend parallel to each other and separate the active area from a memory area of the photodiode.

Abstract: A first side of a tapeless leadframe package is etched to form a ring shaped protrusion and a lead protrusion extending from a base layer. An integrated circuit die is mounted to tapeless leadframe package in flip chip orientation with a front side facing the first side. An electrical and mechanical attachment is made between a bonding pad of the integrated circuit die and the lead protrusion. A mechanical attachment is made between the front side of the integrated circuit die and the ring shaped protrusion. The integrated circuit die and the protrusions from the tapeless leadframe package are encapsulated within an encapsulating block. The second side of the tapeless leadframe package is then etched to remove portions of the base layer and define a lead for a leadframe from the lead protrusion and further define a die support for the leadframe from the ring shaped protrusion.

Abstract: A light projection system includes a MEMS mirror operating on a mirror drive signal to generate a mirror sense signal resulting from operation of the MEMS mirror based on the mirror drive signal. A mirror driver generates the mirror drive signal from a drive control signal. A controller receives the mirror sense signal from the MEMS mirror, obtains a first sample of the mirror sense signal at a first phase thereof, obtains a second sample of the mirror sense signal at a second phase thereof, wherein the first and second phases are separated by a half period of the mirror drive signal, with the second phase occurring after the first phase, and generates the drive control signal based on a difference between the first and second samples to keep the mirror drive signal separated in phase from the mirror sense signal by a desired amount of phase separation.

Abstract: In an embodiment, a method includes: receiving, with a first buffer of a first error compactor unit (ECU), a first memory error packet associated with a first memory; receiving, with the first buffer, a second memory error packet associated with a second memory; transmitting a first reading request for reading the first memory error packet; receiving the first reading request with an arbiter of an error aggregator unit (EAU) of a central memory error management unit (MEMU); in response to receiving the first reading request, reading the first memory error packet from the first buffer, transmitting the first memory error packet to a controller of the central MEMU, and transmitting a first acknowledgement to the first ECU; receiving the first acknowledgement with the first ECU; and in response to receiving the first acknowledgement, transmitting a second reading request for reading the second memory error packet.

Abstract: An integrated optoelectronic or optical device is formed by a polarization-splitting grating coupler including two optical waveguides, a common optical coupler and flared optical transitions between the optical coupler and the optical waveguides. The optical coupler is configured for supporting input/output of optical waves. A first region of the optical coupler lies at a distance from the flared optical transitions. The first region includes a first recessed pattern. Second regions of the optical coupler lie between the first region and the flared optical transitions, respectively, in an adjoining relationship. The second regions include a second recessed pattern different from the first recessed pattern.

Abstract: The present disclosure relates to solutions for operating a flyback converter comprising an active clamp. The flyback converter comprises two input terminals and two output terminals. A first electronic switch and the primary winding of a transformer are connected in series between the input terminals. An active clamp circuit is connected in parallel with the primary winding. The active clamp circuit comprises a series connection of a clamp capacitor and a second electronic switch. A third electronic switch and the secondary winding of the transformer are connected in series between the two output terminals. In particular, the present disclosure relates to solutions for switching the first, second and third electronic switch in order to achieve a zero-voltage switching of the first electronic switch.

Abstract: A start-up phase of a phase lock loop (PLL) circuit includes supplying, by a phase comparator, of control pulses during which an output signal frequency of an oscillator increases. The increase includes an application of a pre-charge current at the oscillator input. A determination is made of a time variation of the output signal frequency. At least one adjustment is made of the intensity of the pre-charge current depending on the at least one determined time variation so as to approach a reference time variation.

Abstract: A MEMS actuator includes a main body having a central portion, couplable to a substrate, and a peripheral portion suspended over the substrate when the central portion is coupled to the substrate. The peripheral portion has a deformable structure extending around the central portion, and forming successively arranged membranes. The MEMS actuator includes bearing structures and corresponding piezoelectric actuators. The bearing structures are fixed at their top to the deformable structure and laterally delimit corresponding cavities, each having a lateral opening facing the central portion of the main body and closed at the top by a membrane. A fixed part of the membrane is fixed to the underlying bearing structure and a suspended part is laterally offset with respect to the underlying bearing structure. The piezoelectric actuators are controllable to cause deformation of the corresponding membrane and rotation of the bearing structures around the central portion of the main body.

Abstract: Memory devices and methods of manufacturing such devices are provided herein. In at least one embodiment, a memory device includes a plurality of phase-change memory cells. An electrically-insulating layer covers lateral walls of each of the phase-change memory cells, and a thermally-insulating material is disposed on the electrically-insulating layer and covers the lateral walls of the phase-change memory cells.

Abstract: A method for evaluating the physical consumption of a polishing pad of a CMP apparatus provided with an eddy current sensor that is configured to sense a distance with a substrate on which a layer to be processed extends. The method includes: generating a magnetic field adapted to induce eddy currents in the layer; acquiring an eddy current signal generated by the layer in response to the magnetic field; calculating an average value of the eddy current signal in the initial time frame; comparing the average value with a pre-set threshold value; and determining a maintenance condition of the polishing pad based on a result of the comparison.

Abstract: A reference current generator circuit generating a reference current that is proportional to absolute temperature as a function of a difference between bias voltages of first and second transistors. A voltage generator generates an input voltage from the reference current by applying the reference current that is proportional to absolute temperature through a plurality of transistors coupled in series between the bias voltage of the second transistor and ground, with the input voltage being generated at a node between given adjacent ones of the plurality of transistors. The input voltage is complementary to absolute temperature. A differential amplifier is biased by a current derived from the reference current and generates a temperature insensitive output reference voltage from the input voltage and a voltage proportional to absolute temperature.

Abstract: A time-interleaved analog to digital converter (TI-ADC) includes a first sub-ADC configured to sample and convert an input analog signal to generate a first digital signal and a second sub-ADC configured to sample and convert said input analog signal to generate a second digital signal. Sampling by the second sub-ADC occurs with a time skew mismatch. A multiplexor interleaves the first and second digital signals to generate a third digital signal. A time skew mismatch error determination circuit processes the first and second digital signals to generate a time error corresponding to the time skew mismatch. A slope value of said third digital signal is determined and multiplied by the time error to generate a signal error. The signal error is summed with the third digital signal to generate a digital output signal which eliminates the error due to the time skew mismatch. This correction is performed in real time.

Abstract: The disclosure relates to integrated circuits including one or more rows of transistors and methods of forming rows of transistors. In an embodiment, an integrated circuit includes a row of bipolar transistors including a first semiconductor layer having a plurality of first conduction regions, a second semiconductor layer having a second conduction region, a common base between the first semiconductor layer and the second semiconductor layer, and a plurality of insulator walls extending in a first direction. The first conduction regions are separated from one another by the insulator walls. The integrated circuit further includes an insulating trench extending in a second direction and in contact with each of the bipolar transistors of the row of bipolar transistors. A conductive layer is coupled to the base, and the conductive layer extends through the insulator walls and extends at least partially into the insulating trench.

Abstract: In some embodiments, a processing system includes at least one hardware block configured to change operation as a function of configuration data, a non-volatile memory including the configuration data for the at least one hardware block, and a configuration module configured to read the configuration data from the non-volatile memory and provide the configuration data read from the non-volatile memory to the at least one hardware block. The configuration module is configured to: receive mode configuration data; read the configuration data from the non-volatile memory; test whether the configuration data contain errors by verifying whether the configuration data are corrupted and/or invalid; and activate a normal operation mode or an error operation mode based on whether the configuration data contain or do not contain errors.

Abstract: A first dielectric layer made of a first dielectric material is deposited over a semiconductor substrate. A buffer layer is then deposited on an upper surface of the first dielectric layer. A trench is opened to extend through the buffer layer and the first dielectric layer. A second dielectric layer made of a second dielectric material is the deposited in a conformal manner on the buffer layer and filling the trench. Chemical mechanical polishing of the second dielectric layer is performed to remove overlying portions of the second dielectric layer with the buffer layer being used as a polish stop. After removing the buffer layer, the first dielectric layer and the second dielectric material filling the trench form a pre-metallization dielectric layer having a substantially planar upper surface.

Abstract: An apparatus includes a digital-to-analog converter coupled in series with a source follower, wherein the digital-to-analog converter is configured to control a current flowing through the source follower, and an amplifier having a first input coupled to a reference generator, a second input coupled to a common node of the source follower and the digital-to-analog converter, and an output coupled to a gate of the source follower.

Abstract: A device includes an AND logic gate and a D latch. The AND logic gate includes a first input configured to be coupled to a third-party device to receive a selection signal, a second input configured to be coupled to the third-party device to receive a status signal, and an output configured to transmit an output signal when the selection signal and the status signal are received. The D latch is capable of storing datum. The D latch includes an activation input coupled to the output of the AND logic gate and a data input configured to be coupled to the third-party device to receive a data signal that is representative of the datum. The D latch is configured to store the datum in response to the output signal.