Patents Assigned to STMicroelectronics (Crolles 2)
  • Integrated photonic interconnect switch and integrated photonic interconnect network
    Patent number: 10830955
    Abstract: A photonic interconnect switch is formed by first and second linear optical waveguides that cross to form an intersection. First and second redirecting photonic ring resonators are coupled together in an intermediate optical coupling zone and are controllable with an electrical signal. The first ring resonator is coupled to the first optical waveguide in a first optical coupling zone. The second ring resonator is coupled to the second optical waveguide in a second optical coupling zone.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: November 10, 2020
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Nicolas Michit, Patrick Le Maitre
  • Integrated circuit and method of manufacturing the same
    Patent number: 10833094
    Abstract: An integrated circuit includes a high-voltage MOS (HV) transistor and a capacitor supported by a semiconductor substrate. A gate stack of the HV transistor includes a first insulating layer over the semiconductor layer and a gate electrode formed from a first polysilicon. The capacitor includes a first electrode made of the first polysilicon and a second electrode made of a second polysilicon and at least partly resting over the first electrode. A first polysilicon layer deposited over the semiconductor substrate is patterned to form the first polysilicon of the gate electrode and first electrode, respectively. A second polysilicon layer deposited over the semiconductor substrate is patterned to form the second polysilicon of the second electrode. Silicon oxide spacers laterally border the second electrode and the gate stack of the HV transistor. Silicon nitride spacers border the silicon oxide spacers.
    Type: Grant
    Filed: April 17, 2018
    Date of Patent: November 10, 2020
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Fausto Piazza, Sebastien Lagrasta, Raul Andres Bianchi, Simon Jeannot
  • IMAGE SENSOR PIXELS HAVING REDUCED PITCH
    Publication number: 20200350355
    Abstract: The present disclosure relates to an image sensor that includes first and second pixels. One or more transistors of the first pixel share an active region with one or more transistors of the second pixel.
    Type: Application
    Filed: April 29, 2020
    Publication date: November 5, 2020
    Applicants: STMICROELECTRONICS (RESEARCH & DEVELOPMENT) LIMITED, STMicroelectronics (Crolles 2) SAS
    Inventors: Jeff M. RAYNOR, Frederic LALANNE, Pierre MALINGE
  • Photonic devices and methods of fabrication thereof
    Patent number: 10823986
    Abstract: A photonic device includes a first region having a first doping type, and a second region having a second doping type, where the first region and the second region contact to form a vertical PN junction. The first region includes a silicon germanium (SiGe) region having a gradual germanium concentration.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: November 3, 2020
    Assignee: STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: Stephane Monfray, Frédéric Boeuf
  • Integrated circuit with vertically structured capacitive element, and its fabricating process
    Patent number: 10818669
    Abstract: A capacitive element includes a trench extending vertically into a well from a first side. The trench is filled with a conductive central section clad with an insulating cladding. The capacitive element further includes a first conductive layer covering a first insulating layer that is located on the first side and a second conductive layer covering a second insulating layer that is located on the first conductive layer. The conductive central section and the first conductive layer are electrically connected to form a first electrode of the capacitive element. The second conductive layer and the well are electrically connected to form a second electrode of the capacitive element. The insulating cladding, the first insulating layer and the second insulating layer form a dielectric region of the capacitive element.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: October 27, 2020
    Assignees: STMicroelectronics (Rousset) SAS, STMicroelectronics (Crolles 2) SAS
    Inventors: Abderrezak Marzaki, Arnaud Regnier, Stephan Niel, Quentin Hubert, Thomas Cabout
  • Method for forming a planarization structure
    Patent number: 10804112
    Abstract: A planarization structure is formed with a planar upper face enclosing a relief projecting from a planar substrate. The process used deposits a layer of a first material over the reliefs and then forms a layer of a second material with a planar upper face. This second material may be etched selectively with respect to the first material. The second layer is processed so that the protuberances of the first material are uncovered. A planarizing is then performed on the first material as far as the layer of the second material by selective chemical-mechanical polishing with respect to the second material.
    Type: Grant
    Filed: May 14, 2018
    Date of Patent: October 13, 2020
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventor: Loic Gaben
  • Method for programming a split-gate memory cell and corresponding memory device
    Patent number: 10796763
    Abstract: A split-gate memory cell includes a state transistor possessing a control gate and a floating gate and a selection transistor possessing a selection gate. The split-gate memory cell is programmed by applying, during a programming duration, a first voltage to the control gate, a second voltage to a drain of the state transistor and a third voltage to the selection gate of the selection transistor. The third voltage is transitioned during the programming duration between a first value and a second value greater than the first value.
    Type: Grant
    Filed: January 24, 2019
    Date of Patent: October 6, 2020
    Assignees: STMicroelectronics (Rousset) SAS, STMicroelectronics (Crolles 2) SAS
    Inventors: Francesco La Rosa, Marc Mantelli, Stephan Niel, Arnaud Regnier
  • Electro-optical phase modulator
    Patent number: 10795189
    Abstract: An electro-optical phase modulator includes a waveguide made from a stack of strips. The stack includes a first strip made of a doped semiconductor material of a first conductivity type, a second strip made of a conductive material or of a doped semiconductor material of a second conductivity type, and a third strip made of a doped semiconductor material of the first conductivity type. The second strip is separated from the first strip by a first interface layer made of a dielectric material, and the third strip is separated from the second strip by a second interface layer made of a dielectric material.
    Type: Grant
    Filed: January 14, 2019
    Date of Patent: October 6, 2020
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventor: Stephane Monfray
  • Detection device, in particular incorporated in a PH meter, and corresponding production process
    Patent number: 10794856
    Abstract: A detection stage of an electronic detection device, for example a pH meter, includes an insulating region that receives an element to be analyzed. The insulating region is positioned on a sensing conductive region. A biasing stage includes an electrically conductive region which is capacitively coupled to the conductive region. The electrically conductive region is formed in an uppermost metallization level along with a further conductive region. That further conductive region is electrically connected to the sensing conductive region by a via passing through an insulating layer which insulates the electrically conductive region from the sensing conductive region.
    Type: Grant
    Filed: February 13, 2019
    Date of Patent: October 6, 2020
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Getenet Tesega Ayele, Stephane Monfray
  • Memory cell comprising a phase-change material
    Patent number: 10797234
    Abstract: A memory cell includes a heating element topped with a phase-change material. Two first silicon oxide regions laterally surround the heating element along a first direction. Two second silicon oxide regions laterally surround the heating element along a second direction orthogonal to the first direction. Top surfaces of the heating element and the two first silicon oxide regions are coplanar such that the heating element and the two first silicon oxide regions have a same thickness.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: October 6, 2020
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventor: Olivier Hinsinger
  • CO-INTEGRATION OF BULK AND SOI TRANSISTORS
    Publication number: 20200303423
    Abstract: An electronic integrated circuit chip includes a first transistor arranged inside and on top of a solid substrate, a second transistor arranged inside and on top of a layer of semiconductor material on insulator having a first thickness, and a third transistor arranged inside and on top of a layer of semiconductor material on insulator having a second thickness. The second thickness is greater than the first thickness. The solid substrate extends underneath the layers of semiconductor material and is insulated from those layers by the insulator.
    Type: Application
    Filed: June 11, 2020
    Publication date: September 24, 2020
    Applicants: STMicroelectronics (Crolles 2) SAS, STMicroelectronics (Rousset) SAS
    Inventors: Jean-Jacques FAGOT, Philippe BOIVIN, Franck ARNAUD
  • Integrated circuit chip with strained NMOS and PMOS transistors
    Patent number: 10777680
    Abstract: Longitudinal trenches extend between and on either side of first and second side-by-side strip areas. Transverse trenches extend from one edge to another edge of the first strip area to define tensilely strained semiconductor slabs in the first strip area, with the second strip area including portions that are compressively strained in the longitudinal direction and/or tensilely strained in the transverse direction. In the first strip area, N-channel MOS transistors are located inside and on top of the semiconductor slabs. In the second strip area, P-channel MOS transistors are located inside and on top of the portions.
    Type: Grant
    Filed: August 7, 2019
    Date of Patent: September 15, 2020
    Assignees: STMicroelectronics (Crolles 2) SAS, Commissariat A L'Energie Atomique et aux Energies Alternatives
    Inventors: Remy Berthelon, Francois Andrieu
  • Method of etching a cavity in a stack of layers
    Patent number: 10770306
    Abstract: A cavity is etched in a stack of layers which includes a first layer made of a first material and a second layer made of a second material. To etch the cavity, a first etch mask having a first opening is formed over the stack of layer. The stack of layers is then etched through the first opening to a depth located in the second layer. A second mask having a second opening, the dimensions of which are smaller, in top view, than the first opening, is formed over the stack of layer. The second opening is located, in top view, opposite the area etched through the first opening. The second layer is then etched through the second opening to reach the first layer. The etch method used is configured to etch the second material selectively over the first material.
    Type: Grant
    Filed: January 4, 2019
    Date of Patent: September 8, 2020
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Pierre Bar, Francois Leverd, Delia Ristoiu
  • Measurement of the duration of a pulse
    Patent number: 10771048
    Abstract: A first circuit includes a first chain of identical stages defining first and second delay lines. A second circuit includes a second chain of identical stages defining third and fourth delay lines. The stages of the second chain are identical to the stages of the first chain. A third circuit selectively couples one of the third delay line, the fourth delay line, or a first input of the third circuit to an input of the first circuit.
    Type: Grant
    Filed: January 20, 2020
    Date of Patent: September 8, 2020
    Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics SA
    Inventors: Capucine Lecat-Mathieu De Boissac, Fady Abouzeid, Gilles Gasiot, Philippe Roche, Victor Malherbe
  • Integrated circuit with improved resistive region
    Patent number: 10770357
    Abstract: An integrated circuit includes a semiconductor substrate with an electrically isolated semiconductor well. An upper trench isolation extends from a front face of the semiconductor well to a depth located a distance from the bottom of the well. Two additional isolating zones are electrically insulated from the semiconductor well and extending inside the semiconductor well in a first direction and vertically from the front face to the bottom of the semiconductor well. At least one hemmed resistive region is bounded by the two additional isolating zones, the upper trench isolation and the bottom of the semiconductor well. Electrical contacts are electrically coupled to the hemmed resistive region.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: September 8, 2020
    Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics (Rousset) SAS
    Inventors: Benoit Froment, Stephan Niel, Arnaud Regnier, Abderrezak Marzaki
  • Random number generator
    Patent number: 10754618
    Abstract: A random number generation device includes conductive lines including interruptions and a number of conductive vias. A via is located at each interruption. Each via randomly fills or does not fill the interruption. A circuit is capable of determining the electric continuity or lack of continuity of the conductive lines.
    Type: Grant
    Filed: July 16, 2018
    Date of Patent: August 25, 2020
    Assignees: STMicroelectronics (Rousset) SAS, STMicroelectronics (Crolles 2) SAS
    Inventors: Benoit Froment, Sebastien Petitdidier, Mathieu Lisart, Jean-Marc Voisin
  • GERMANIUM-ON-SILICON LASER IN CMOS TECHNOLOGY
    Publication number: 20200266609
    Abstract: A germanium waveguide is formed from a P-type silicon substrate that is coated with a heavily-doped N-type germanium layer and a first N-type doped silicon layer. Trenches are etched into the silicon substrate to form a stack of a substrate strip, a germanium strip, and a first silicon strip. This structure is then coated with a silicon nitride layer.
    Type: Application
    Filed: May 6, 2020
    Publication date: August 20, 2020
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Mathias PROST, Moustafa EL KURDI, Philippe BOUCAUD, Frederic BOEUF
  • PHOTODIODE
    Publication number: 20200266310
    Abstract: A photodiode include a first substrate layer of a first dopant type and a second substrate layer of a second dopant type on top of the first substrate layer. Semiconductor walls are provided in a semiconductor substrate which includes the first and second substrate layers. The semiconductor walls include: two outer semiconductor walls and at least one inside semiconductor wall positioned between the two outer semiconductor walls. Each inside semiconductor wall is located between two semiconductor walls having longer length.
    Type: Application
    Filed: February 13, 2020
    Publication date: August 20, 2020
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Boris RODRIGUES GONCALVES, Arnaud TOURNIER
  • OPTO ELECTRICAL TEST MEASUREMENT SYSTEM FOR INTEGRATED PHOTONIC DEVICES AND CIRCUITS
    Publication number: 20200256759
    Abstract: An optical testing circuit on a wafer includes an optical input configured to receive an optical test signal and photodetectors configured to generate corresponding electrical signals in response to optical processing of the optical test signal through the optical testing circuit. The electrical signals are simultaneously sensed by a probe circuit and then processed. In one process, test data from the electrical signals is simultaneously generated at each step of a sweep in wavelength of the optical test signal and output in response to a step change. In another process, the electrical signals are sequentially selected and the sweep in wavelength of the optical test signal is performed for each selected electrical signal to generate the test data.
    Type: Application
    Filed: April 30, 2020
    Publication date: August 13, 2020
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Philippe GROSSE, Patrick LE MAITRE, Jean-Francois CARPENTIER
  • Thermo-electric generator
    Patent number: 10741740
    Abstract: A thermo-electric generator includes a semiconductor membrane with a phononic structure containing at least one P-N junction. The membrane is suspended between a first support designed to be coupled to a cold thermal source and a second support designed to be coupled to a hot thermal source. The structure for suspending the membrane has an architecture allowing the heat flux to be redistributed within the plane of the membrane.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: August 11, 2020
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Emmanuel Dubois, Jean-Francois Robillard, Stephane Monfray, Thomas Skotnicki