Abstract: An integrated image sensor with backside illumination includes a pixel. The pixel is formed by a photodiode within an active semiconductor region having a first face and a second face. A converging lens, lying in front of the first face of the active region, directs received light rays towards a central zone of the active region. At least one diffracting element, having a refractive index different from a refractive index of the active region, is provided at least partly aligned with the central zone at one of the first and second faces.

Abstract: A multi-stage ring oscillator generates an output clock signal having a frequency which is dependent on a digitally leakage current that is applied to each stage of the multi-stage ring oscillator. A magnitude of a leakage current sourced by each digitally controlled leakage current source is set by a control circuit in response to a selection signal. A calibration circuit processes a reference clock signal and the output clock signal generated by the multi-stage ring oscillator to make adjustment to the selection signal which drives a locking of a frequency of the output clock signal to a desired frequency.

Abstract: A bipolar transistor is supported by a single-crystal silicon substrate including a collector contact region. A first epitaxial region forms a collector region of a first conductivity type on the collector contact region. A second epitaxial region forms a base region of a second conductivity type. Deposited semiconductor material forms an emitter region of the first conductivity type. The collector region, base region and emitter region are located within an opening formed in a stack of insulating layers that includes a sacrificial layer. The sacrificial layer is selectively removed to expose a side wall of the base region. Epitaxial growth from the exposed sidewall forms a base contact region.

Abstract: A strip made of a semiconductor material is formed over a substrate. Longitudinal portions of the strip having a same length are covered with sacrificial gates made of an insulating material and spaced apart from each other. Non-covered portions of the strip are doped to form source/drain regions. An insulating layer followed by a layer of a temporary material is then deposited. Certain ones of the sacrificial gates are left in place. Certain other ones of the sacrificial gates are replaced by a metal gate structure. The temporary material is then replaced with a conductive material to form contacts to the source/drain regions.

Abstract: A device for monitoring a critical path of an integrated circuit includes a replica of the critical path formed by sequential elements mutually separated by delay circuits that are programmable though a corresponding main multiplexer. A control circuit controls delay selections made by each main multiplexer. A sequencing module operates to sequence each sequential element using a main clock signal by delivering, in response to a main clock signal, respectively to the sequential elements, secondary clock signals that are mutually time shifted in such a manner as to take into account the propagation time inherent to the main multiplexer.

Abstract: A bipolar transistor is supported by a single-crystal silicon substrate including a collector connection region. A first epitaxial region forms a collector region doped with a first conductivity type on the collector connection region. The collector region includes a counter-doped region of a second conductivity type. A second epitaxial region forms a base region of a second conductivity type on the first epitaxial region. Deposited semiconductor material forms an emitter region of the first conductivity type on the second epitaxial region. The collector region, base region and emitter region are located within an opening formed in a stack of insulating layers that includes a sacrificial layer. The sacrificial layer is selectively removed to expose a side wall of the base region. Epitaxial growth from the exposed sidewall forms a base contact region.

Abstract: A photonic integrated device includes a first waveguide and a second waveguide. The first and second waveguides are mutually coupled at a junction region which includes a bulge region. The bulge region is defined two successive etching operations using two distinct etch masks, where the first etching operation is a partial etch and the second etching operation is a complete etch.

Abstract: An integrated circuit is provided, including: a first pair including a first nMOS transistor and a first pMOS transistor; a second pair including a second nMOS transistor and a second pMOS transistor; the first and the second nMOS transistors including a channel region made of silicon that is subjected to tensile stress, and their respective gates being positioned at least 250 nm from a border of their active zone; and a third pair including a third nMOS transistor having a same construction as the second nMOS transistor and a third pMOS transistor having a same construction as the first pMOS transistor and having a tensile stress that is lower by at least 250 MPa than the tensile stress of the channel region, respective gates of the transistors of the third pair being positioned at most 200 nm from a border of their active zone.

Abstract: A three-dimensional integrated structure is formed by a first substrate with first components oriented in a first direction and a second substrate with second components oriented in a second direction. An interconnection level includes electrically conducting tracks that run in a third direction. One of the second direction and third direction forms a non-right and non-zero angle with the first direction. An electrical link formed by at least one of the electrically conducting tracks electrically connected two points of the first or of the second components.

Abstract: An image sensor chip includes a semiconductor layer intended to receive illumination on a back face and comprising a matrix of pixels on a front face. An interconnection structure is arranged on the front face and a carrier is attached to the interconnection structure with a first face of the carrier facing the front face. An annular trench, arranged on a perimeter of the image sensor chip, extends from a second face of the carrier through an entire thickness of the carrier and into the interconnection structure. A via opening, arranged within the annual trench, extends from the second face of the carrier through the entire thickness of the carrier to reach a metal portion of the interconnection structure. The via opening an annual trench are lined with an insulating layer. The via opening include a metal conductor making an electrical connection to the metal portion.

Abstract: A transformer of the balanced-unbalanced type includes a primary inductive circuit and a secondary inductive circuit housed inside an additional inductive winding connected in parallel to the terminals of the secondary circuit and inductively coupled with the primary circuit and the secondary circuit.

Abstract: The application relates to an integrated circuit with SRAM memory and provided with several superimposed levels of transistors, the integrated circuit including SRAM cells provided with a first transistor and a second transistor belonging to an upper level of transistors and each having a double gate composed of an upper electrode and a lower electrode laid out on either side of a semiconductor layer, a lower gate electrode of the first transistor being connected to a lower gate electrode of the second transistor.

Abstract: A semiconductor substrate doped with a first doping type is positioned adjacent an insulated gate electrode that is biased by a gate voltage. A first region within the semiconductor substrate is doped with the first doping type and biased with a bias voltage. A second region within the semiconductor substrate is doped with a second doping type that is opposite the first doping type. Voltage application produces an electrostatic field within the semiconductor substrate causing the formation of a fully depleted region within the semiconductor substrate. The fully depleted region responds to absorption of a photon with an avalanche multiplication that produces charges that are collected at the first and second regions.

Abstract: An integrated circuit of the BiCMOS type includes at least one vertical junction field-effect transistor. The vertical junction field-effect transistor is formed to include a channel region having a critical dimension of active surface that is controlled by photolithography. A gate region of the transistor is formed by two spaced apart first trenches in that are filled with a doped semiconductor material, wherein the two spaced apart first trenches bound the channel region and set the critical dimension.

Abstract: An optical waveguide is configured to propagate a light signal. Metal vias are arranged along and on either side of a portion of the optical waveguide. Additional metal vias are further arranged along and on either side of the optical waveguide both upstream and downstream of the portion of the optical waveguide. The metal vias and additional metal vias are oriented orthogonal to a same plane, the same plane being orthogonal to a transverse cross-section of the portion of the optical waveguide.

Abstract: A method for determining a margin of use of an integrated circuit includes monitoring at least one sensor so as to determine at least one physical parameter representative of use of the integrated circuit, evaluating the at least one physical parameter to determine an instantaneous state of aging of the integrated circuit as a function of the at least one physical parameter, and calculating the margin of use for the integrated circuit from a comparison of the instantaneous state of aging with a presumed state of aging. If operation of the integrated circuit is outside the margin of use, at least one operating performance point of the integrated circuit is adjusted so as to bring operation of the integrated circuit back within the margin of use.

Abstract: An optical waveguide termination device includes a waveguide and metal vias surrounding an end portion of the waveguide. The end portion of the waveguide has a transverse cross-sectional area that decreases towards its distal end. The metal vias are orthogonal to a same plane, with the same plane being orthogonal to the transverse cross-section. The metal vias absorb light originating from the end portion when a light signal propagates through the waveguide, and the metal vias and the end portion provide that an effective index of an optical mode to be propagated through the waveguide progressively varies in the end portion. Additional metal vias may be present along the waveguide upstream of the end portion, with the additional metal vias bordering the waveguide upstream of the end portion providing that the effective index of an optical mode to be propagated through the waveguide varies progressively toward the end portion.

Abstract: An integrated circuit includes a semiconductor substrate with an electrically isolated semiconductor well. An upper trench isolation extends from a front face of the semiconductor well to a depth located a distance from the bottom of the well. Two additional isolating zones are electrically insulated from the semiconductor well and extending inside the semiconductor well in a first direction and vertically from the front face to the bottom of the semiconductor well. At least one hemmed resistive region is bounded by the two additional isolating zones, the upper trench isolation and the bottom of the semiconductor well. Electrical contacts are electrically coupled to the hemmed resistive region.

Abstract: Longitudinal trenches extend between and on either side of first and second side-by-side strips. Transverse trenches extend from one edge to another edge of the first strip to define tensilely strained semiconductor slabs in the first strip, with the second strip including portions that are compressively strained in the longitudinal direction and/or tensilely strained in the transverse direction. In the first strip, N-channel MOS transistors are located inside and on top of the semiconductor slabs. In the second strip, P-channel MOS transistors are located inside and on top of the portions.

Abstract: A semiconductor body of a first conductivity type and doped with a first doping level includes, at a front side surface thereof, a well of a second conductivity type and a region doped with the first conductivity type at a second doping level greater than the first doping level. An insulated vertical gate structure separates the region from the well. Buried iInsulated electrodes extend from the front side surface completely through the well and into a portion of the semiconductor body underneath the well. A conductive material portion of each buried insulated electrode is configured to receive a bias voltage and a conductive material portion of insulated vertical gate structure is configured to receive a gate voltage. The semiconductor body is delimited by a capacitive deep trench isolation that is biased at the same voltage as the buried insulated electrode.