Patents Assigned to STMicroelectronics France
  • Patent number: 12288080
    Abstract: System, method, and circuitry for generating content for a programmable computing device based on user-selected configuration information. A settings registry is generated based on the user's selections. The settings registry and the user selected configuration information is utilized to generate the content, such as code, data, parameters, settings, etc. When the content is provided to the programmable computing device, the content initializes, configures, or controls one or more software and hardware aspects of the programmable computing device, such as boot sequence configurations, internal peripheral configurations, states of the programmable computing device, transitions between states of the programmable computing device, etc., and various combinations thereof.
    Type: Grant
    Filed: August 29, 2022
    Date of Patent: April 29, 2025
    Assignees: STMicroelectronics France, STMICROELECTRONICS (ROUSSET) SAS, STMicroelectronics (Grand Quest) SAS
    Inventors: Emmanuel Grandin, Nabil Safi, Maxime Dortel, Laurent Meunier, Frederic Ruelle
  • Publication number: 20250123766
    Abstract: System, method, and circuitry for simulating a memory architecture to generate a bin image of a file tree for a memory embedded on a programmable computing device. A memory configuration of the memory and a file tree identifying a file structure to be used in the memory are obtained. A bin image of a file system for the memory is generated based on the memory configuration and the file tree using a memory simulator and a file-management-system manager. The bin image is provided to the programmable computing device for storage in the memory.
    Type: Application
    Filed: December 19, 2024
    Publication date: April 17, 2025
    Applicant: STMicroelectronics France
    Inventors: Zouhaier AOUAINI, Haithem RAHMANI
  • Patent number: 12270842
    Abstract: In an embodiment method for detecting the phase of an analog signal via a hybrid coupler operating in a power-combiner mode, the hybrid coupler comprises a first input intended to receive the analog signal, a second input intended to receive a reference signal having a reference phase and the same frequency as the analog signal, and two outputs, and is configured to generate, at these two outputs, a first output signal and a second output signal, respectively. The embodiment method comprises measuring peak values of the analog signal, of the reference signal, and of at least one of the first and second output signals, calculating the phase shift between the phase of the analog signal and the reference phase depending on the measured peak values, and determining the phase of the analog signal depending on the calculated phase shift and the reference phase.
    Type: Grant
    Filed: January 22, 2019
    Date of Patent: April 8, 2025
    Assignees: STMicroelectronics France, CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE, UNIVERSITE DE BORDEAUX, INSTITUT POLYTECHNIQUE DE BORDEAUX
    Inventors: Vincent Knopik, Jeremie Forest, Eric Kerherve
  • Patent number: 12256156
    Abstract: The method for processing a matrix of pixels each containing an original red, green, blue, or infrared component, comprises at least one interpolation of an interpolated component different from the original component of a pixel of interest from the components of a group of pixels neighboring the pixel of interest. The interpolation comprises: a calculation of the sum of the components of reference pixels weighted by a respectively assigned weight, the reference pixels being pixels of the group having the same original component as the interpolated component, an evaluation of the spatial uniformity of an environment, within the group of each reference pixel, a calculation of the weights assigned to the reference pixels at values which are normalized and proportional to the respective spatial uniformity.
    Type: Grant
    Filed: September 8, 2022
    Date of Patent: March 18, 2025
    Assignee: STMicroelectronics France
    Inventor: Pol Perrin
  • Patent number: 12249991
    Abstract: A clock generator circuit includes an oscillator circuit coupled to a bias circuit. The bias circuit includes a current mirror, third and fourth transistors, and a cascode transistor. The current mirror includes a reference transistor and a set of copy transistors that are programmable. The third transistor has a source connected to a cold spot, a drain and a gate connected to this drain. The fourth transistor has a source connected to the drain of the third transistor, a drain, and a gate connected to that drain. The cascode transistor has a source connected to a drain of at least one of the copy transistors, a drain, and a gate connected to the gate of the fourth transistor. The gates of the fourth transistor and the cascode transistor are thicker than the gates of the reference transistor, each copy transistor, and the third transistor.
    Type: Grant
    Filed: June 30, 2023
    Date of Patent: March 11, 2025
    Assignee: STMicroelectronics France
    Inventors: Laurent Jean Garcia, Marc Houdebine
  • Publication number: 20250077240
    Abstract: System, method, and circuitry for generating content for a programmable computing device based on user-selected configuration information. A settings registry is generated based on the user's selections. The settings registry and the user selected configuration information is utilized to generate the content, such as code, data, parameters, settings, etc. When the content is provided to the programmable computing device, the content initializes, configures, or controls one or more software and hardware aspects of the programmable computing device, such as boot sequence configurations, internal peripheral configurations, states of the programmable computing device, transitions between states of the programmable computing device, etc., and various combinations thereof.
    Type: Application
    Filed: November 15, 2024
    Publication date: March 6, 2025
    Applicants: STMicroelectronics (Grand Ouest) SAS, STMicroelectronics France
    Inventors: Frederic RUELLE, Laurent MEUNIER, Bechir JABRI, Emmanuel GRANDIN, Nabil SAFI, Ghaith OUESLATI, Yohann MARTINIAULT, Jerome CAILLET
  • Patent number: 12243937
    Abstract: The disclosure concerns a device which comprises a stack of two high electron mobility transistors, referred to as first and second transistor, separated by an insulating layer and each provided with a stack of semiconductor layers respectively referred to as first stack and second stack, the first and the second stack each comprising, from the insulating layer to, respectively, a first and a second surface, a barrier layer and a channel layer, the first and the second transistor respectively comprising a first set of electrodes and a second set of electrodes, the first and the second set of electrodes each comprising a source electrode, a drain electrode, and a gate electrode which are arranged so that the first and the second transistor are electrically connected head-to-tail.
    Type: Grant
    Filed: April 1, 2022
    Date of Patent: March 4, 2025
    Assignees: STMicroelectronics France, STMicroelectronics International N.V.
    Inventors: Matthieu Nongaillard, Thomas Oheix
  • Patent number: 12210758
    Abstract: System, method, and circuitry for simulating a memory architecture to generate a bin image of a file tree for a memory embedded on a programmable computing device. A memory configuration of the memory and a file tree identifying a file structure to be used in the memory are obtained. A bin image of a file system for the memory is generated based on the memory configuration and the file tree using a memory simulator and a file-management-system manager. The bin image is provided to the programmable computing device for storage in the memory.
    Type: Grant
    Filed: April 29, 2022
    Date of Patent: January 28, 2025
    Assignee: STMicroelectronics France
    Inventors: Zouhaier Aouaini, Haithem Rahmani
  • Patent number: 12190123
    Abstract: System, method, and circuitry for generating content for a programmable computing device based on user-selected configuration information. A settings registry is generated based on the user's selections. The settings registry and the user selected configuration information is utilized to generate the content, such as code, data, parameters, settings, etc. When the content is provided to the programmable computing device, the content initializes, configures, or controls one or more software and hardware aspects of the programmable computing device, such as boot sequence configurations, internal peripheral configurations, states of the programmable computing device, transitions between states of the programmable computing device, etc., and various combinations thereof.
    Type: Grant
    Filed: August 29, 2022
    Date of Patent: January 7, 2025
    Assignees: STMicroelectronics France, STMicroelectronics (Grand Quest) SAS
    Inventors: Frederic Ruelle, Laurent Meunier, Bechir Jabri, Emmanuel Grandin, Nabil Safi, Ghaith Oueslati, Yohann Martiniault, Jerome Caillet
  • Patent number: 12192652
    Abstract: An embodiment method for estimating a missing or incorrect value in a table of values generated by a photosite matrix comprises a definition of a zone of the table comprising the value to be estimated and other values, referred to as neighboring values, and an estimation of the value to be estimated based on the primary neighboring values and the weight associated with these primary neighboring values, wherein a weight of each neighboring value, referred to as primary neighboring value, of the same colorimetric component as that of the missing or incorrect value to be estimated, is determined according to differences between neighboring values disposed on an axis and neighboring values disposed parallel with this axis and positioned in relation to this axis on the same side as the primary neighboring value for which the weight is determined.
    Type: Grant
    Filed: October 6, 2023
    Date of Patent: January 7, 2025
    Assignee: STMicroelectronics France
    Inventors: Valentin Rebiere, Antoine Drouot
  • Patent number: 12184289
    Abstract: In an embodiment a radiofrequency doubler includes a first transistor and a second transistor connected in parallel between a first differential output and a first terminal of a current source configured to provide a bias current, a second terminal of the current source being connected to a first supply potential, a third transistor connected between the first terminal of the current source and a second differential output, a circuit configured to apply an AC component of a first differential input and a first DC voltage to a gate of the first transistor, apply an AC component of a second differential input and the first DC voltage to a gate of the second transistor and apply a second DC voltage to a gate of the third transistor, and a feedback loop configured to control the first voltage or the second voltage from a difference between DC components of the first and second differential outputs so as to equalize the DC components.
    Type: Grant
    Filed: October 23, 2023
    Date of Patent: December 31, 2024
    Assignee: STMicroelectronics France
    Inventor: Lionel Vogt
  • Publication number: 20240413228
    Abstract: A cell includes a Z-PET-type structure that is formed with two front gates extending over an intermediate region between an anode region and a cathode region. The individual front gates of the two front gates are spaced apart by a distance that is shorter than 40% of a width of each individual front gate.
    Type: Application
    Filed: August 20, 2024
    Publication date: December 12, 2024
    Applicant: STMicroelectronics France
    Inventor: Philippe GALY
  • Patent number: 12167142
    Abstract: In an embodiment an apparatus includes a scanning photographic sensor configured to acquire an image, according to an integration time of the sensor, of a scene illuminated with periodically emitted light pulses by a source, so that the image has a regular succession of bands with different luminosities when the integration time of the sensor is different from a period of the light pulses, a processor configured to generate a signature vector representative of the regular succession of bands with different luminosities being present in the image acquired by the photographic sensor, wherein the signature vector is independent of a reflectance of an objects of the scene and of a level of light in the scene, determine a frequency of the bands in the image on basis of the generated signature vector and determine the period of the pulses of the source on basis of the determined frequency of the bands in the image, and a controller configured to adjust the integration time of the photographic sensor so that the int
    Type: Grant
    Filed: June 24, 2022
    Date of Patent: December 10, 2024
    Assignees: STMicroelectronics (Research & Development) Limited, STMicroelectronics France
    Inventors: Arnaud Bourge, Tanguy Le Dauphin, Antoine Drouot, Brian Douglas Stewart
  • Patent number: 12164316
    Abstract: An electronic device includes a near-field communication module and a powering circuit for delivering a power supply voltage to the near-field communication module. When the near-field communication module is in a low power mode, the powering circuit is configured for an operational mode where it is periodically started to provide the power supply voltage.
    Type: Grant
    Filed: March 9, 2023
    Date of Patent: December 10, 2024
    Assignees: STMicroelectronics (Rousset) SAS, STMicroelectronics France, STMicroelectronics (Alps) SAS
    Inventors: Alexandre Tramoni, Florent Sibille, Patrick Arnould
  • Publication number: 20240385808
    Abstract: System, method, and circuitry for generating a linker model for use by a toolchain associated with a programmable computing device. One or more regions in the memory resources available to the programmable computing devices is defined for used by an application executing on the programmable computing device. One or more sections is defined for those regions for use by the application. Resource boundaries are generated for the application based on the defined regions and the defined sections. A user is enabled to modify the defined regions or the defined sections or the generated resource boundaries. A linker model is then generated based on the available memory resources, the defined regions, the defined sections, and the generated resource boundaries. This linker model is then utilized to generate a linker script for the programmable computing device based the linker syntax compatible with a toolchain linker for the programmable computing device.
    Type: Application
    Filed: June 14, 2024
    Publication date: November 21, 2024
    Applicant: STMicroelectronics France
    Inventor: Tarek BOCHKATI
  • Patent number: 12143719
    Abstract: A method includes dividing a field of view into a plurality of zones and sampling the field of view to generate a photon count for each zone of the plurality of zones, identifying a focal sector of the field of view and analyzing each zone to select a final focal object from a first prospective focal object and a second prospective focal object.
    Type: Grant
    Filed: September 20, 2023
    Date of Patent: November 12, 2024
    Assignees: STMicroelectronics France, STMicroelectronics, Inc., STMicroelectronics (Research & Development) Limited
    Inventors: Darin K. Winterton, Donald Baxter, Andrew Hodgson, Gordon Lunn, Olivier Pothier, Kalyan-Kumar Vadlamudi-Reddy
  • Patent number: 12141590
    Abstract: System, method, and circuitry for generating content for a programmable computing device based on user-selected configuration information. A settings registry is generated based on the user's selections. The settings registry and the user selected configuration information is utilized to generate the content, such as code, data, parameters, settings, etc. When the content is provided to the programmable computing device, the content initializes, configures, or controls one or more software and hardware aspects of the programmable computing device, such as boot sequence configurations, internal peripheral configurations, states of the programmable computing device, transitions between states of the programmable computing device, etc., and various combinations thereof.
    Type: Grant
    Filed: August 29, 2022
    Date of Patent: November 12, 2024
    Assignees: STMicroelectronics (Grand Ouest) SAS, STMicroelectronics France
    Inventors: Frederic Ruelle, Emmanuel Grandin, Bechir Jabri
  • Patent number: 12125894
    Abstract: A bipolar transistor includes a collector. The collector is formed by: a first portion of the collector which extends under an insulating trench, and a second portion of the collector which crosses through the insulating trench. The first and second portions of the collector are in physical contact.
    Type: Grant
    Filed: October 26, 2023
    Date of Patent: October 22, 2024
    Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics France
    Inventors: Alexis Gauthier, Pascal Chevalier
  • Patent number: 12117942
    Abstract: A processing system includes a communication system and a processing core configured to generate write requests. A circuit has associated a slave interface circuit configured to manage an address sub-range and selectively forward write requests addressed to a given address. Configuration data specifies whether the given address is protected/unprotected and locked/unlocked. In response to a received write request, address and data are extracted and a determination based on the configuration data is made as to whether the extracted address is protected/unprotected, and locked/unlocked. When the extracted address is unprotected or unlocked, the slave interface forwards the write request. When the extracted address is protected and locked, the slave interface generates an unlock signal in response to a comparison of the extracted address with the extracted data, with the unlock signal being asserted when the extracted data satisfy a predetermined rule with respect to the extracted address.
    Type: Grant
    Filed: February 14, 2023
    Date of Patent: October 15, 2024
    Assignees: STMicroelectronics S.r.l., STMicroelectronics France
    Inventors: Roberta Vittimani, Federico Goller, Riccardo Angrilli, Charles Aubenas
  • Patent number: 12100752
    Abstract: A cell includes a Z2-FET-type structure that is formed with two front gates extending over an intermediate region between an anode region and a cathode region. The individual front gates of the two front gates are spaced apart by a distance that is shorter than 40% of a width of each individual front gate.
    Type: Grant
    Filed: July 14, 2021
    Date of Patent: September 24, 2024
    Assignee: STMicroelectronics France
    Inventor: Philippe Galy