Abstract: According to one aspect, an integrated circuit includes: an electronic module configured to generate a voltage at an output, and an electronic control circuit coupled to an output of the electronic module, the electronic control circuit comprising an emissive electronic component. The electronic control circuit is configured to cause the emissive electronic component to emit light radiation as a function of a value of the voltage at the output of the electronic module relative to a value of an operating voltage of the electronic module, and the operating voltage is specific thereto during normal operation of this electronic module. The light radiation emitted by the emissive electronic component is configured to diffuse to an outer face of the integrated circuit.

Abstract: A method includes processing, by an arithmetic and logic unit of a processor, masked data, and keeping, by the arithmetic and logic unit of the processor, the masked data masked throughout their processing by the arithmetic and logic unit. A processor includes an arithmetic and logic unit configured to keep masked data masked throughout processing of the masked data in the arithmetic and logic unit.

Abstract: The transmission device comprising a transmit stage configured to deliver a transmission signal on an input-output node of an antenna and comprising a power transistor coupled to the input-output node and configured to amplify a signal to be transmitted. The device comprises a receive stage configured to receive a reception signal on the input-output node and comprising an attenuator circuit configured to attenuate the reception signal. The attenuator circuit comprising the power transistor and a control circuit able to place the power transistor in a triode mode.

Abstract: A system, such as a System-on-Chip includes an interface component or PLUG which generates transactions over an IP block, such as an interconnect serving one or more clients via virtual channels. The client or clients are mapped onto the virtual channels via client/virtual channel mappings. The virtual channels are provided as a first set of virtual channels in the interface component which cooperate with a second set of virtual channels in the IP block. First and second client/virtual channel mappings for the first set of virtual channels and the second set of virtual channels are provided. The first and second client/virtual channel mappings are separately programmable and mutually decoupled from one another.

Abstract: The disclosure relates to a method for reconstruction of a three-dimensional image of an object. A first image is acquired of the object lit by a luminous flux having, in a region including the object, a luminous intensity dependant on the distance, with a light source emitting the luminous flux. A second image is acquired of the object lit by a luminous flux having, in a region including the object, a constant luminous intensity. For each pixel of a three-dimensional image, a relative distance of a point of the object is determined as a function of the intensity of a pixel corresponding to the point of the object in each of the acquired images.

Abstract: An embodiment of the present invention discloses a system and method for decoding multiple independent encoded audio streams using a single decoder. The system includes one or more parsers, a preprocessor, an audio decoder, and a renderer. The parser extracts individual audio frames from each input audio stream. The preprocessor combines the outputs of all parsers into a single audio frame stream and enables sharing of the audio decoder among multiple independent encoded audio streams. The audio decoder decodes the single audio frame stream and provides a single decoded audio stream. And the renderer renders the individual reconstructed audio streams from the single decoded audio stream.

Abstract: A multi-layer substrate has a front face with external pads. An integrated-circuit chip is positioned inside of the multi-layer substrate. An electronic and/or electric component is also positioned inside of the substrate above the integrated-circuit chip. An electrical connection network is formed in the multi-layer substrate to selectively connect the integrated-circuit chip and component together and to the external pads. A first screen is positioned within the multi-layer substrate between the integrated-circuit chip and the electrical connection network, this first screen being connected by vias to the external pads. A second screen is position on a top (external) surface of the multi-layer substrate above the component and electrical connection network, this second screen being connected by vias to the external pads. The integrated-circuit chip is position to be inside the first and second screens.

Abstract: An SRAM memory device including a plurality of memory cells arranged in a plurality of rows and a plurality of columns; each row of memory cells is adapted to store a RAM word; the RAM word includes a corresponding data word, a corresponding ECC word to be used for error detection and correction purposes and a corresponding applicative word to be used during debugging operations. The SRAM memory device further includes a configurable port adapted to receive a RAM word and to program corresponding memory cells of a selected row based on the received RAM word during a writing access of the SRAM memory device. The SRAM memory device further includes a memory controller unit including circuitry for selectively configuring the configurable port in one among a plurality of modes.

Abstract: A source of photons resulting from a recombination of localized excitons, including a semiconductor layer having a central portion surrounded with heavily-doped regions; above said central portion, a layer portion containing elements capable of being activated by excitons, coated with a first metallization; and under the semiconductor layer, a second metallization of greater extension than the first metallization. The distance between the first and second metallizations is on the order of from 10 to 60 nm; and the lateral extension of the first metallization is on the order of from ?0/10*ne to ?0/2*ne, where ?0 is the wavelength in vacuum of the emitted light and ne is the effective refractive index of the mode formed in the cavity created by the two metallizations.

Abstract: A method for transmitting messages from first units of an integrated circuit to at least one second unit of the integrated circuit. The first units generate first digital messages and transform them into second digital messages obtained by application of an orthogonal or quasi-orthogonal transformation to the first messages. The second messages of the first units are added up and transmitted to the second unit.

Abstract: A backside illumination semiconductor image sensor, wherein each photodetection cell includes a semiconductor body of a first conductivity type of a first doping level delimited by an insulation wall, electron-hole pairs being capable in said body after a backside illumination; on the front surface side of said body, a ring-shaped well of the second conductivity type, this well delimiting a substantially central region having its upper portion of the first conductivity type of a second doping level greater than the first doping level; and means for controlling the transfer of charge carriers from said body to said upper portion.

Abstract: A trimmable resistor for use in an integrated circuit is trimmed using a heater. The heater is selectively coupled to a voltage source. The application of voltage to the heater causes the heater temperature to increase and produce heat. The heat permeates through a thermal separator to the trimmable resistor. The resistance of the trimmable resistor is permanently increased or decreased when the temperature of the resistor is increased to a value within a particular range of temperatures.

Abstract: Processing method for modulated data transmitted in the form of multiplexed frames (Frame 1, . . . Frame 10) containing symbols that have a symbol frequency. The method comprises a frame selection processing operation performed at least partly at a working frequency below the symbol frequency, and a demodulation processing operation comprising at least a part performed at the working frequency on the selected frames.

Abstract: A method for searching a digital transmission having unknown carrier and symbol frequencies in a modulated reception signal, includes performing successive trials of several carrier and symbol frequencies, using decreasing values of the symbol frequency, demodulating the reception signal with the tried carrier frequency, filtering the demodulated signal in a band having a width corresponding to the currently tried symbol frequency, and producing samples of the filtered signal. For each currently tried symbol frequency, forming a complex indicator having a real component and an imaginary component established from the successive samples of the filtered signal such that they have cyclostationary properties and that one of the components tends to cancel when the other component tends towards a relative maximum, building the spectrum of the variation of the complex indicator, searching for a singular spike in the spectrum, and determining the real symbol frequency from the frequency of the spike.

Abstract: A synchronization system includes a memory and a control circuit. The control circuit includes a write interface for writing data in said memory with a first clock signal, wherein the write interface is configured for operating with a write pointer in response to a write command, a read interface for reading data from said memory with a second clock signal, wherein the read interface is configured for operating with a read pointer in response to a read command, a synchronization circuit for synchronizing said write pointer and said read pointer with a synchronization latency, and an elaboration circuit for elaborating data in memory with an elaboration latency, wherein the elaboration latency is smaller than the synchronization latency.

Abstract: An RF amplifier including first and second branches coupled in parallel between first and second supply voltage terminals, and a differential pair including first and second transistors each having first and second main current terminals, the second main current terminal of the first transistor being coupled by a first capacitor to the first main current terminal of the second transistor, and the second main current terminal of the second transistor being coupled by a second capacitor to the first main current terminal of the first transistor, wherein the first branch includes a first resistor coupled between the first main current terminal to of the first transistor and the second capacitor, and the second branch includes a second resistor; coupled between the first main current terminal of the second transistor and the first capacitor.

Abstract: A trimmable resistor for use in an integrated circuit is trimmed using a heater. The heater is selectively coupled to a voltage source. The application of voltage to the heater causes the heater temperature to increase and produce heat. The heat permeates through a thermal separator to the trimmable resistor. The resistance of the trimmable resistor is permanently increased or decreased when the temperature of the resistor is increased to a value within a particular range of temperatures.

Abstract: An analog switch including at least one first MOS transistor capable of transferring a signal from a first terminal to a second terminal; a connection circuit for bringing a substrate terminal of the first transistor to a voltage which is a function of the voltages of the first and second terminals; and a circuit for controlling a control voltage of the first transistor with the signal.

Abstract: A method may compensate for direct current (DC) offset in a radio frequency reception device. The method may include partitioning an analog portion of the reception device into a plurality of zones, for each zone, calibrating initial DC offset compensation to be applied within an operating range of a respective zone, the operating range of the other zones being limited to a threshold operating range, and determining DC offset compensation to be applied to the reception device throughout the operating range based on the basic DC offset compensations.

Abstract: An RF amplifier including first and second branches coupled in parallel between first and second supply voltage terminals, and a differential pair including first and second transistors each having first and second main current terminals, the second main current terminal of the first transistor being coupled by a first capacitor to the first main current terminal of the second transistor, and the second main current terminal of the second transistor being coupled by a second capacitor to the first main current terminal of the first transistor, wherein the first branch includes a first resistor coupled between the first main current terminal of the first transistor and the second capacitor, and the second branch includes a second resistor; coupled between the first main current terminal of the second transistor and the first capacitor.