Abstract: An integrated semiconductor heating assembly includes a semiconductor substrate, a chamber formed therein, and an exit port in fluid communication with the chamber, allowing fluid to exit the chamber in response to heating the chamber. The integrated heating assembly includes a first heating element adjacent the chamber, which can generate heat above a selected threshold and bias fluid in the chamber toward the exit port. A second heating element is positioned adjacent the exit port to generate heat above a selected threshold, facilitating movement of the fluid through the exit port away from the chamber. Addition of the second heating element reduces the amount of heat emitted per heating element and minimizes thickness of a heat absorption material toward an open end of the exit port. Since such material is expensive, this reduces the manufacturing cost and retail price of the assembly while improving efficiency and longevity thereof.

Abstract: Disclosed herein is a sensor chip including at least one sensing device and a control circuit. The control circuit is configured to receive configuration data as input, and acquire data from the at least one sensing device in accordance with the configuration data. The control circuit classifies a context of the at least one sensing device relative to its surroundings based on analysis of the acquired data in accordance with the configuration data.

Abstract: An electronic device includes a printed circuit board (PCB) having at least one conductive trace thereon. A system on chip (SoC) is mounted on the PCB and electrically coupled to the conductive trace. A sensor chip is mounted on the PCB in a spaced apart relation with the SoC and electrically coupled to the conductive trace such that the sensor chip and SoC are electrically coupled. The sensor chip includes an accelerometer and/or a gyroscope, and a control circuit. The control circuit is configured to receive configuration data as input, acquire data from the accelerometer and/or the gyroscope. The control circuit is also configured to process the data so as to generate a context of the electronic device relative to its surroundings, the processing being performed in using a processing technique operating in accordance with the configuration data, and output the context.

Abstract: An electronic device described herein includes a sensing unit having at least one sensor to acquire sensing data. An associated computing device extracts sensor specific features from the sensing data, and generates a motion activity vector, a voice activity vector, and a spatial environment vector as a function of the sensor specific features. The motion activity vector, voice activity vector, and spatial environment vector are processed to determine a base level context of the electronic device relative to its surroundings, with the base level context having aspects each based on the motion activity vector, voice activity vector, and spatial environment vector. Meta level context of the electronic device relative to its surroundings is determined as a function of the base level context, with the meta level context being at least one inference made from at least two aspects of the plurality of aspects of the base level context.

Abstract: Gain offset and voltage offset compensation for a controllable gain element of a circuit is effected in response to a gain offset value and voltage offset value. A current operating condition of the circuit is sensed and compared to a nominal operating condition. If the current operating condition is outside the nominal operating condition by more than a threshold, a calibration operation to set the gain and voltage offset values is performed. The gain offset value is selected as a function of the sensed current operating condition. With respect to the voltage offset, differential input terminals of the controllable gain element are shunted and the output is measured. The measured output value of the controllable gain element is applied as the voltage offset value. The operating conditions at issue may be one or more of supply voltage and temperature.

Abstract: Method of making at least one transistor strained channel semiconducting structure, comprising steps to form a sacrificial gate block and insulating spacers arranged in contact with the lateral faces of the sacrificial gate block, form sacrificial regions in contact with the lateral faces of said semiconducting zone, said sacrificial regions being configured so as to apply a strain on said semiconducting zone, remove said sacrificial gate block between said insulating spacers, replace said sacrificial gate block by a replacement gate block between said insulating spacers, remove said sacrificial regions, and replace said sacrificial regions by replacement regions in contact with the lateral faces of said semiconducting zone, on a semiconducting zone that will form a transistor channel region.

Abstract: Disclosed herein is a microfluidic jetting device having a piezoelectric member positioned above a displaceable membrane. A voltage is applied across the piezoelectric member causing deformation of the piezoelectric member. The deformation of the piezoelectric member results in a displacement of the membrane, which is formed above a cavity. Displacement of the membrane creates pressure to jet or eject liquid from the cavity and suction liquid into the cavity through ports or apertures formed in the in membrane.

Abstract: An embodiment of a motor controller includes a motor driver and a signal conditioner. The motor driver is operable to generate a motor-coil drive signal having a first component at a first frequency, and the signal conditioner is coupled to the motor driver and is operable to alter the first component. For example, if the first component of the motor-coil drive signal causes the motor to audibly vibrate (e.g., “whine”), then the signal conditioner may alter the amplitude or phase of the first component to reduce the vibration noise to below a threshold level.

Abstract: A method for making a semiconductor device includes forming laterally spaced-apart semiconductor fins above a substrate. At least one dielectric layer is formed adjacent an end portion of the semiconductor fins and within the space between adjacent semiconductor fins. A pair of sidewall spacers is formed adjacent outermost semiconductor fins at the end portion of the semiconductor fins. The at least one dielectric layer and end portion of the semiconductor fins between the pair of sidewall spacers are removed. Source/drain regions are formed between the pair of sidewall spacers.

Abstract: A fin of silicon-germanium material is formed and covered with an epitaxially grown layer of silicon material. A dummy transistor gate is then formed to extend over a channel of the fin. Sidewall spacers are formed on each side of the dummy transistor gate and directly on top of the expitaxial silicon layer. Epitaxially grown raised source and drain regions are formed on each side of the dummy transistor gate adjacent the sidewall spacers. The dummy transistor gate and a portion of the epitaxial silicon layer (underneath said dummy transistor gate) are removed and replaced by a metal gate.

Abstract: An analog integrated circuit is disclosed in which short channel transistors are stacked on top of long channel transistors, vertically separated by an insulating layer. With such a design, it is possible to produce a high density, high power, and high performance analog integrated circuit chip including both short and long channel devices that are spaced far enough apart from one another to avoid crosstalk. In one embodiment, the transistors are FinFETs and the long channel devices are multi-gate FinFETs. In one embodiment, single and dual damascene devices are combined in a multi-layer integrated circuit cell. The cell may contain various combinations and configurations of the short and long-channel devices. A high density cell can be made by simply shrinking the dimensions of the cells and replicating two or more cells in the same size footprint as the original cell.

Abstract: A system and method for correcting errors in an ECC block using soft-decision data. In an embodiment, a soft-decision ECC decoding method, uses “soft” data indicative of how reliable bits of data are when read out. Such a method may use an update module for receiving and manipulating the soft-decision data and iteratively change bits or groups of bits based upon an ordering of the reliability factors. Then a calculator module may determine the total number of errors still remaining after each iteration. Determining just the total number of errors instead of the actual locations is far less computationally intensive, and therefore, many combination of potential flip-bit combination may be analyzed quickly to determine if any combination might reduce the total number of errors enough to be handled by the conventional hard-decision ECC decoding method.

Abstract: A multi-fin FINFET device may include a substrate and a plurality of semiconductor fins extending upwardly from the substrate and being spaced apart along the substrate. Each semiconductor fin may have opposing first and second ends and a medial portion therebetween, and outermost fins of the plurality of semiconductor fins may comprise an epitaxial growth barrier on outside surfaces thereof. The FINFET may further include at least one gate overlying the medial portions of the semiconductor fins, a plurality of raised epitaxial semiconductor source regions between the semiconductor fins adjacent the first ends thereof, and a plurality of raised epitaxial semiconductor drain regions between the semiconductor fins adjacent the second ends thereof.

Abstract: A method for forming fins includes growing a SiGe layer and a silicon layer over a surface of a bulk Si substrate, patterning fin structures from the silicon layer and the SiGe layer and filling between the fin structures with a dielectric fill. Trenches are formed to expose end portions of the fin structures. A first region of the fin structures is blocked off. The SiGe layer of the fin structures of a second region is removed by selectively etching the fin structures from the end portions to form voids, which are filled with dielectric material. The silicon layer of the fin structures is exposed. The SiGe layer in the first region is thermally oxidized to drive Ge into the silicon layer to form SiGe fins on an oxide layer in the first region and silicon fins on the dielectric material in the second region.

Abstract: Psychoacoustic bass audio signal enhancement can be accomplished using a monotonic, asymmetric polynomial distortion. A non-linear process applies a monotonic, asymmetric polynomial distortion function that has continuous first and second derivatives to generate even and odd harmonics of missing fundamental frequencies. This polynomial distortion produces the desired psychoacoustic effect with a fairly rapid rolloff so as to avoid unpleasant aliasing. Moreover, the lack of first-order discontinuities prevents clicks or glitches.

Abstract: A method for making a semiconductor device may include forming a dummy gate above a semiconductor layer on an insulating layer, forming sidewall spacers above the semiconductor layer and on opposing sides of the dummy gate, forming source and drain regions on opposing sides of the sidewall spacers, and removing the dummy gate and underlying portions of the semiconductor layer between the sidewall spacers to provide a thinned channel region having a thickness less than a remainder of the semiconductor layer outside the thinned channel region. The method may further include forming a replacement gate stack over the thinned channel region and between the sidewall spacers and having a lower portion extending below a level of adjacent bottom portions of the sidewall spacers.

Abstract: A method of making an inkjet print head may include forming, by sawing with a rotary saw blade, continuous slotted recesses in a first surface of a wafer. The continuous slotted recesses may be arranged in parallel, spaced apart relation, and each continuous slotted recess may extend continuously across the first surface. The method may further include forming discontinuous slotted recesses in a second surface of the wafer to be aligned and coupled in communication with the continuous slotted recesses to define alternating through-wafer channels and slotted recess portions. The method may further include selectively filling the residual slotted recess portions to define through-wafer ink channels.

Abstract: A braking intensity indicator system for a vehicle of a type that includes a foot operated brake pedal and at least one brake light may include a proximity sensor to be associated with the brake pedal and a controller. The controller may be configured to cooperate with the proximity sensor to determine a plurality of brake pedal positions versus time during foot operation of the brake pedal, and selectively adjust an intensity of the at least one brake light based upon the determined plurality of brake pedal positions versus time.

Abstract: A thermoelectric device includes a plurality of thin-film thermoelectric elements. Each thin-film thermoelectric element is a Seebeck-Peltier device. The thin-film thermoelectric elements are electrically coupled in parallel with each other. The thermoelectric device may be fabricated using conventional semiconductor processing technologies and may be a thin-film type device.

Abstract: An AC/DC converter includes a first terminal and a second terminal for receiving an AC voltage and a third terminal and a fourth terminal for delivering a DC voltage. A capacitive circuit is connected between the third and fourth terminals. A rectifying bridge circuit has input terminals respectively coupled to the first and second terminals and has output terminal respectively connected to the third and fourth terminals. An inductive element is coupled in series with a first switch circuit between the first terminal and an input terminal of the rectifying bridge circuit.