Abstract: A method is for estimating drift between a first clock used in a digital transmission processing of a first Ultra Wide Band (UWB) pulse train signal and a second clock used in a digital reception processing of a second UWB pulse train signal resulting from a transmission of the first UWB pulse train signal. The method may include sampling the second UWB pulse train signal, and calculating trellis information representative of a trellis having reference paths respectively associated to different reference values of the drift and including sample transitions of a sampled third signal from the sampled second UWB pulse train signal. The method may further include processing the sampled third signal along the trellis for obtaining a path metric for each processed reference path, and selecting the processed reference path having a greatest path metric, the drift being the reference value associated to the selected processed reference path.
Abstract: Semiconductor protection devices, and related methods and systems, especially devices for providing series current limiting. The device typically comprises two regenerative building blocks and/or MOSFETs connected back-to-back in series, where one of the MOSFETs/Regenerative Building Blocks has an extra voltage probe electrode that provides a regenerative signal with self-limited voltage to the other via coupling to its gate electrode.
Type:
Application
Filed:
May 3, 2010
Publication date:
March 3, 2011
Applicants:
STMicroelectronics N.V.
Inventors:
Alexei Ankoudinov, Vladimir Rodov, Richard A. Blanchard
Abstract: The block de-interleaving system includes an input for receiving a set of time-aligned blocks or interleaved data, physical memory unit, and a de-interleaving block for writing the blocks in the memory in a first predetermined manner and reading the blocks from the memory in a second predetermined manner to de-interleave the data of the blocks. The physical memory unit may include several different physical memories, and the de-interleaving block is adapted to completely write and read a block into and from one physical elementary memory.
Abstract: To control a decoding latency, larger blocks are nonequally segmented into smaller ones. The decoding process starts directly after reception of the first small block. The latency is defined by the latency of the last small block decoding. Changing the number of iterations during the turbo-code decoding also permits control of the decoding latency.
Abstract: A calibration is performed tone per tone during interframe spacing. A peak detection is used for measuring the level of the corresponding signal, and a gain correction coefficient is stored for correcting the digital complex modulation coefficients provided by the mapping.
Type:
Grant
Filed:
March 15, 2007
Date of Patent:
September 28, 2010
Assignee:
STMicroelectronics N.V.
Inventors:
Chiara Cattaneo, Philippe Rouzet, Régis Cattenoz, Patrick Conti
Abstract: Method for transmitting information in a multi-band OFDM system, comprising delivering according to a given communication standard an initial data stream (IDS), splitting (11) said initial data stream into a chosen number of elementary data streams and simultaneously transmitting (12) said elementary data streams according to said communication standard on said communication medium (MD) within different respective sub-bands (SBi). These sub-bands all blong to the same band group. Proposal based on the MBOA standard.
Abstract: The LDPC decoder includes a processor for updating messages exchanged iteratively between variable nodes and check nodes of a bipartite graph of the LDPC code. The decoder architecture is a partly parallel architecture clocked by a clock signal. The processor includes P processing units. First variable nodes and check nodes are mapped on the P processing units according to two orthogonal directions. The decoder includes P main memory banks assigned to the P processing units for storing all the messages iteratively exchanged between the first variable nodes and the check nodes. Each main memory bank includes at least two single port memory partitions and one buffer the decoder also includes a shuffling network and a shift memory.
Type:
Grant
Filed:
March 2, 2006
Date of Patent:
August 10, 2010
Assignee:
Stmicroelectronics N.V.
Inventors:
Norbert Wehn, Frank Kienle, Torben Brack
Abstract: A prototype system having an integrated circuit including an on-chip processor and an on-chip router connected to off-chip resources via an interface. A request directing unit on the chip receives memory access requests and directs them in accordance with either one of two address maps. In one of the address maps, a first range of addresses is allocated to at least one on-chip resource and a second range of addresses is allocated to the interface. In the other memory address map, the first range of addresses is also allocated to the interface. An integrated circuit including such a request directing unit is also described, together with a method for evaluating a prototype system.
Abstract: A method for processing a digital signal includes an elementary processing including a radiofrequency transposition with a radiofrequency transposition signal and a digital to analog conversion of the transposed digital signal for delivering a radiofrequency analog signal. The digital to analog conversion is controlled by a control signal and a power control signal, the control signal having a frequency twice the frequency of the radiofrequency transposition signal. Each transition of the radiofrequency transposition signal occurs between two consecutive pulses of said control signal.
Abstract: The method is for decoding an LDPC encoded codeword, the LDPC code being represented by a bipartite graph between check nodes and variable nodes including first variable nodes and second variable nodes connected to the check nodes by a zigzag connectivity. The method includes updating messages exchanged iteratively between variable nodes and check nodes including a first variable processing phase during which all the messages from the first variable nodes to the check nodes are updated and a check nodes processing phase during which all the messages from the check nodes to the first variable nodes are updated. The check nodes processing phase further includes updating all the messages from the second variable nodes to the check nodes, and directly passing an updated message processed by a check node to the next check node through the zigzag connectivity.
Type:
Grant
Filed:
March 2, 2006
Date of Patent:
July 6, 2010
Assignee:
STMicroelectronics N.V.
Inventors:
Norbert Wehn, Frank Kienle, Torben Brack
Abstract: The transmission band of an analog signal to be transmitted is notched, including sub-carriers to be modulated from digital modulation coefficients respectively associated with the sub-carriers. The method includes providing an initial digital signal from successive frequency-domain groups each containing the digital modulation coefficients respectively associated to the sub-carriers. The initial signal is filtered with a frequency resolution greater than the frequency resolution of the frequency-domain groups to remove frequencies corresponding to the sub-carriers to be removed. The filtered signal is windowed using a windowing mask having a representation in the frequency-domain including a main lobe and secondary lobes. The power spectrum of the lobes decrease faster than the inverse of the frequency squared.
Abstract: A method for writing and reading data in a main nonvolatile memory having target pages in which data are to be written and read, the method including providing a nonvolatile buffer having an erased area, providing a volatile cache memory, and receiving a write command to update a target page with updating data the length of which can be lower than the length of a page. The method also includes, in response to the write command, writing the updating data into the erased area of the nonvolatile buffer, together with management data of a first type, and recording an updated version of the target page in the cache memory or updating in the cache memory a previously updated version of the target page.
Abstract: A TFA (thin film on ASIC) image sensor with stability-optimized photodiode for converting electromagnetic radiation into an intensity-dependent photocurrent. The TFA includes an intermetal dielectric layer, pixel back electrodes, vias, metal contacts, a transparent conductive oxide (TCO) layer, and an intrinsic absorption layer with a thickness between 300 nm and 600 nm. The pixel back electrodes are disposed over the intermetal dielectric layer, which is disposed over the ASIC. The vias connect to the pixel back electrodes and the metal contacts, which are formed in the intermetal dielectric layer. The TCO is disposed above the intrinsic absorption layer, which is disposed above the pixel back electrodes.
Type:
Grant
Filed:
October 19, 2007
Date of Patent:
April 20, 2010
Assignee:
STMicroelectronics N.V.
Inventors:
Peter Rieve, Marcus Walder, Konstantin Seibel, Jens Prima, Arash Mirhamed
Abstract: A Bluetooth master unit polls a slave unit to enable the slave to resynchronize to the master, by sending POLL packets with sufficient frequency to maintain a connection to the slave, and in the intervals between such packets, sending NULL packets with sufficient frequency to maintain synchronization of the slave. By replacing some POLL packets with NULL packets, since the slave does not have to respond to a NULL packet, it can save some power, and there is reduced interference on other piconets. The frequency of the remaining POLL packets is set according to a Link Supervision Timeout (to avoid having this timer expire and thus keep the Bluetooth Link to the slave alive) and according to the time since the master received the last packet from the slave.
Abstract: A method for detecting an eventual channel intended to a designated user equipment among n channels received by the designated user equipment during a given duration, each channel received during the duration carrying encoded data masked with an identifier associated to a user equipment. The method includes a selecting phase having a demasking step demasking the received masked encoded data of each channel with the identifier of the designated user equipment, a decoding step decoding the demasked encoded data of each channel to obtain a set of digital decoded data for each channel, a calculating step calculating, from each set of digital decoded data, a global information representative of a confidence in digital data received on the physical channel, and a detecting step detecting the channel from all the global information.
Abstract: A method processes defects in a radio frequency transmission subsystem due to elements therein. The defects may include mismatch between two channels in phase quadrature in the transmission subsystem and a transposition signal leaking from a first frequency transposition stage of the transmission subsystem. The method may include calibration processing including estimating compensation parameters representative of the defects. The estimating may include delivering, into the transmission subsystem upstream of the elements creating the defects, a reference signal having a reference frequency, obtaining, downstream of the first transposition stage, of a resultant reference signal, and obtaining, from the resultant reference signal, of an approximate value for each compensation parameter. The method also may include compensating for the defects by injecting the approximate values into the transmission subsystem.
Type:
Application
Filed:
July 20, 2009
Publication date:
February 25, 2010
Applicants:
STMicroelectronics N.V., STMicroelectronics (Grenoble) SAS
Abstract: A method may compensate for direct current (DC) offset in a radio frequency reception device. The method may include partitioning an analog portion of the reception device into a plurality of zones, for each zone, calibrating initial DC offset compensation to be applied within an operating range of a respective zone, the operating range of the other zones being limited to a threshold operating range, and determining DC offset compensation to be applied to the reception device throughout the operating range based on the basic DC offset compensations.
Type:
Application
Filed:
July 20, 2009
Publication date:
January 28, 2010
Applicants:
STMicroelectronics SA, STMicroelectronics N.V., STMicroelectronics (Grenoble) SAS
Inventors:
Antoine HUE, Gabriel DELLA-MONICA, Florent SIBILLE
Abstract: A method may compensate for direct current (DC) offset in a radio frequency reception device. The method may include partitioning an analog portion of the reception device into a plurality of zones, for each zone, calibrating initial DC offset compensation to be applied within an operating range of a respective zone, the operating range of the other zones being limited to a threshold operating range, and determining DC offset compensation to be applied to the reception device throughout the operating range based on the basic DC offset compensations.
Type:
Application
Filed:
July 20, 2009
Publication date:
January 28, 2010
Applicants:
STMicroelectronics SA, STMicroelectronics N.V., STMicroelectronics (Grenoble) SAS
Inventors:
Antoine HUE, Gabriel Della-Monica, Florent Sibille
Abstract: A Bluetooth master radio frequency unit addresses a slave radio frequency unit, to enable the slave to synchronize to the master, by sending poll packets and optionally null packets over an active link, the master being arranged so that receipt of a response from the slave unit to a poll packet is sufficient to maintain the active link. The slave unit does not have to respond to all of the poll packets. This approach can allow the slave to preserve more (transmit) power by going into a deep sleep mode in which a low power oscillator may be used while still allowing the master unit to detect whether the slave has resynchronized or not (and thus to update a Link Supervision Timer, for example).
Abstract: An embodiment of an amplifier circuit comprising a succession of amplification stages having at least a first amplification stage receiving a first signal and a second amplification stage downstream of the first amplification stage; a stage of unity gain capable of receiving the first signal and of providing a second signal corresponding to the low-impedance copy of the first signal; and a third amplification stage having its input connected to the output of the stage of unity gain by a capacitor and having its output connected to the output of the second amplification stage.