Abstract: An integrated test device reduces external wiring congestion to a memory. The integrated test device provides for separate decoder testing and debugging to find specific errors in the memory. The device also helps in reducing the complexity of the test of external BIST. Furthermore, the number of clock cycles required for the decoder testing for an N-address memory is reduced from 4N cycles to N clock cycles. Additionally, the access time for the memory is reduced as the test device is used as a pipelining device in normal operation mode.

Abstract: A Programmable Logic Device provides efficient scalability for configuration memory programming while requiring reduced area for implementation. The device includes an array of configuration memory cells, a Vertical Shift Register (VSR) connected to the vertical lines of the array of configuration memory cells, a Select Register (SR) connected to the horizontal lines of the array of configuration memory cells, a Horizontal Shift Register (HSR) providing the enable input to the Select Register (SR), and a Configuration State Machine (CSM) which synchronizes the operations of the VSR, SR and HSR.

Abstract: A method and an improved FPGA apparatus for enabling the selective deployment of unused flip-flops or other circuit elements in IO cells and unused decoders or other circuit elements in Look Up Tables (LUT), for core logic functions is provided, comprising disconnecting means for selectively disconnecting unused circuit elements from the IO pad circuitry or from said LUT circuitry, and connecting means for selectively connecting said disconnected circuit elements either to the connection matrix of the core logic or between themselves to provide independently configured functions.

Abstract: An Input Output Block (IOB) provides programmable hysteresis to support multiple IO standards including a differential amplifier having one input coupled to an input signal and its second input coupled to a complementary input signal in the case of differential signalling, or to a reference voltage for the case of single-ended signalling, a pair of series coupled digital inverters coupled to one output of said differential amplifier, one or more transistors coupled in parallel with each input transistor of the differential amplifier, each transistor of each parallel coupled set being of a different size relative to the corresponding input transistor, the control terminal of each parallel coupled transistor in each set being coupled to the output of one of said series coupled inverters such that positive feedback is provided directly or indirectly through a selection switch, and hysteresis control bits that symmetrically enable or disable each said selection switch to provide a programmable level of hysteresis

Abstract: An improved Programmable Logic Device architecture that provides more efficient utilization of resources by enabling access to defined circuit elements in the domain of any Programmable Logic Block (PLB) from any other PLB in the device, by incorporating a connecting means in the routing structure for selectively connecting the input or output of the circuit element in the domain of the PLB to the common interconnect matrix connecting all the PLBs together.

Abstract: A FPGA device that includes a plurality of programmable logic blocks connected to each other through interconnect resources, one or more sets of registers connected to the interconnect resources for configuring the programmable logic blocks. Additional logic is provided with the registers for selecting an interconnect/logic block testing mode thereby enabling a rapid interconnect/logic testing.

Abstract: An apparatus for enabling duty cycle locking at the rising/falling edge of the clock includes a counter that receives a gated input clock. A lock detector receives an input clock for generating control signals. An address decoder is connected to the counter for generating a set of selection signals. A first multiplexer includes select lines connected to receive the selection signals. A plurality of delay chains provide multiple output taps with a first delay chain connected to the first multiplexer. A second multiplexer is connected to one of the plurality of delay chains with its select lines being hard wired. A latch is connected to the output of the first multiplexer and the second multiplexer for providing the output.

Abstract: An area efficient data shifter/rotator using a barrel shifter. The invention is a circuit, which uses a single barrel shifter and is controllable to implement either a left or right shift or rotation of bits of a digital data word. The circuit is dynamically controllable to implement left or right shift of bits of the digital data word (both logical and arithmetic) and rotation (to the left or right) of bits of the word. The proposed circuit produces the required output in a single cycle.

Abstract: An improved Built-In-Self-Test (BIST) architecture for Content Addressable Memory (CAM) devices, including a bit scanner for reading out the contents of the matchlines of the CAM cells as a serial bit stream; a bit transition detector that detects and determines the address of each bit transition in the serial bit stream; a state machine that generates bit addresses for each expected transition in the serial bit stream; and an analyser that compares expected transition bit addresses with detected transition addresses and declares a BIST failure if expected and detected transition addresses do not match at any point in the bit stream.

Abstract: A CMOS to PECL voltage level converter includes a pad driver containing drive compensation circuitry and a feedback circuit for sensing the output drive level and providing control signals to the drive compensation circuitry for compensating for temperature and process variations while minimizing power consumption.

Abstract: A transceiver provides a high-speed transmission signal using shared resources and reduced area. A differential amplifier has its current source/sink connected to a supply terminal. A multiplexing circuit is configured to connect an input of the differential amplifier to an I/O pad so as to output a received input/output signal to internal integrated circuit logic during one mode, or alternatively connect an output of the differential amplifier to the I/O pad so as to output a signal received from the internal integrated circuit logic for input/output during another mode. A level translation operation on the signal may be performed with respect to outputting the signal received from the internal integrated circuit logic.

Abstract: A method for mapping an electronic digital circuit to a Look Up table (LUT) based Programmable Logic Deviceoperates by selecting an unmapped or partially mapped LUT, and identifying a group of circuit elements for mapping on the selected LUT based on the available capacity of the selected LUT and the mapping constraints. The identified circuit elements are mapped onto the selected LUT. The identification of circuit elements and mapping is carried out while taking into consideration the Cascade Logic associated with the selected LUT. The process continues until all circuit elements have been mapped. The group of circuit elements is mapped to the cascade logic prior to mapping on the LUTs. Conversely, the cascade logic is incorporated only after all circuit elements have initially been mapped onto LUTs or some elements remain unmapped after all LUTs have been utilized. The mapping constraints include timing, placement, and size constraints.

Abstract: The present invention provides an improved Chua's circuit providing current mode operation, access to all state variables, minimum use of grounded passive elements, and freedom from passive component matching comprising a dual output current conveyer based inductor having one grounded terminal, a capacitor connected across the second terminal of said inductor, a resistor having one terminal connected to the second terminal of said inductor, the second terminal of said resistor connected to one terminal of a second capacitor the other end of which is grounded, and a pair of dual output current conveyers connected together to form a 2-terminal negative resistance having one terminal connected to ground and the second terminal connected to the second terminal of said resistance.

Abstract: A method and system for reducing power consumption in digital circuits using charge redistribution include a plurality of signal lines, an intermediate floating virtual source/sink, and a charge redistribution circuit connected to each signal line that isolates the signal line from its source and connects it to the intermediate floating virtual source/sink during an idle period prior to a change of state. This charge redistribution provides steady state statistical independent advantage due to charge recycling without inserting extra complimentary lines.

Abstract: A phase generator includes a phase-shift enable and disable signal generator connected to configuration bits at its first input and connected to a reset signal at its reset input for generating a control signal; the configuration bits corresponding to the phase shift desired. The phase generator includes a logic signal generation device connected at its control input to the output of the phase-shift enable and disable signal generator and connected to a reset signal at its reset input for providing a phase generating signal; and a feedback element connected between the output of the logic signal generation device and control input of the phase-shift enable and disable signal generator for providing controlled clock signal to the phase-shift enable and disable signal generator.

Abstract: A Programmable Logic Device providing reduction in power consumption for sequential logic and data storage functions, including at least one circuit arrangement configurable to function as a dual-edge-triggered flip-flop operating on a selected one or both edges of the circuit clock.

Abstract: Output buffers which operate at high speeds require delicate handling of the noise on the supply lines. This necessitates control be exercised over current slew rate not only on the rising edge of current but also on the falling edge of the current. A circuit provides control over the current slew rate on the falling edge in high speed output driver charging/discharging heavy load without affecting the speed of the driver (which otherwise would have created supply/ground bounce due to parasitics present in the bonding wires, package pins and on-chip metal interconnects in the I/O ring). The control circuit further suppresses the supply/ground noise by a very significant level while incurring small penalty in terms of silicon area and power dissipation. This circuit includes a CMOS circuit that is cross-coupled input connected to the output buffer input signals with a dummy capacitance coupled to the CMOS circuit output.

Abstract: A first order temperature compensated reference current generator includes a current device providing a controlled current, a startup circuit connected to the current device for initiating operation of the current device, and a current definition mechanism driven by the current device for supplying a current which is independent of temperature, process and individual temperature coefficients circuit elements used. The current definition mechanism incorporates voltage controlled resistors driven by a predetermined voltage and having a predetermined temperature coefficient.

Abstract: An area efficient realization of an N-bit constant coefficient adder/subtractor implemented on FPGAs, utilizing N LUTs with single output generation capability. It includes three inputs from every LUT for addition/subtraction, without any requirement for extra logic for support of arithmetic mode and carry chains. For FPGAs supporting 4-input LUTs, the concept is further enhanced with the capability to perform addition and subtraction dynamically, by exploiting the fourth unused input of the LUTs. Another embodiment involves delay-optimized realization of an N-bit constant coefficient adder/subtractor implemented on FPGAs with 4-input LUTs. LUTs in the implementation have single output generation capability without any carry generation and propagation. The implementation utilizes N+1 LUTs and gives a delay proportional to N/2 of routing resource used. However, the implementation becomes more efficient by the use of cascade chains. The delay optimization is achieved by doing computation in two parallel chains.

Abstract: The present invention provides a programmable logic device with reduced power consumption comprising, a first set of data storage elements, at least a first power supply connected to the said first set of data storage elements, a second set of substantially identical interconnected tiles, each including logic blocks, at least a second power supply independent of the said first power supply connected to said identical tiles wherein said second power supply is switched-off when the logic block is not being used.