Abstract: The present invention provides an improved Chua's circuit providing current mode operation, access to all state variables, minimum use of grounded passive elements, and freedom from passive component matching comprising a dual output current conveyer based inductor having one grounded terminal, a capacitor connected across the second terminal of said inductor, a resistor having one terminal connected to the second terminal of said inductor, the second terminal of said resistor connected to one terminal of a second capacitor the other end of which is grounded, and a pair of dual output current conveyers connected together to form a 2-terminal negative resistance having one terminal connected to ground and the second terminal connected to the second terminal of said resistance.

Abstract: An FFT/IFFT processor having computation logic capable of processing butterfly operations, and storage for storing the operands of butterfly operations, including a mechanism for storing the operands of multiple consecutive butterfly operations in contiguous storage locations and wherein the computation logic is capable of simultaneously accessing and processing said multiple butterfly operations.

Abstract: An LCD display driver provides adjustable contrast independent of multiplexing requirements by generating each COM signal in a time slot of a repeating signal frame, with each COM signal containing one or more active periods and one or more inactive periods. The relative time proportions of these periods are adjustable. Corresponding SEGMENT signals turn on/off required segments while maintaining an essentially zero DC component. The logic levels and the relative active time and inactive times of the COM and segment signals being adjustable for increasing or decreasing the RMS voltage levels across the LCD element as desired.

Abstract: A Content Addressable Memory (CAM) with an improved the priority encoder enabling random storage of CIDR IP addresses in memory, including a plurality of data storage elements each having a first compare circuit for comparing a search key with the content of the data storage elements, the data storage elements storing data and associated prefix lengths; a match line associated with each first compare circuit to receive a signal representing a match or a mismatch of the compare data; and a priority encoder that receives match line signals and prefix lengths from data storage elements and provides a memory location address that corresponds to the matched longest prefix.

Abstract: A Programmable Logic Device provides efficient scalability for configuration memory programming while requiring reduced area for implementation. The device includes an array of configuration memory cells, a Vertical Shift Register (VSR) connected to the vertical lines of the array of configuration memory cells, a Select Register (SR) connected to the horizontal lines of the array of configuration memory cells, a Horizontal Shift Register (HSR) providing the enable input to the Select Register (SR), and a Configuration State Machine (CSM) which synchronizes the operations of the VSR, SR and HSR.

Abstract: An improved low voltage to high voltage translator for digital electronic circuits providing reduced rise times, fall times and transition times that remain independent of operating conditions. This is accomplished by modifying a conventional low-to-high voltage translator to include a switched active pull-up at the output of the first high-voltage switch, controlled by the input low-voltage signal and gated by the output from the low-to-high-voltage translator and a switched active pull-down at the output of the first high-voltage switch, controlled by the input low-voltage signal and gated by the complement of the output from the low-to-high-voltage translator, so as at to provide regenerative pull-up and pull-down that also counteracts the bootstrap capacitance at the output of the first high-voltage switch.

Abstract: A sense amplifier includes a feedback controlled bit line access scheme that feeds a sense amplifier output signal back to control operation of its associated bit line access transistor. This feedback may be implemented using a pair of inverter circuits each coupling a respective output signal to the control gate of the associated access transistor. Alternatively, the feedback may be implement using a logic gate which logically combines the sense amplifier output signals together to generate an output signal for controlling operation of both access transistors. The logic gate is preferably a NAND gate. The sense amplifier further includes a cross-connected feedback inversion circuit which inverts a sense amplifier output signal from a first latch inverter for application to a conducting line of a second latch inverter.

Abstract: A CMOS to PECL voltage level converter includes a pad driver containing drive compensation circuitry and a feedback circuit for sensing the output drive level and providing control signals to the drive compensation circuitry for compensating for temperature and process variations while minimizing power consumption.

Abstract: An FPCA includes a scheme for peripheral routing that provides symmetrical routing across its entire area including the periphery by incorporating peripheral routing lines of equal length that are symmetrically deflected orthogonally. The symmetrical peripheral routing lines are connected to switch boxes and connection boxes at the periphery for maintaining constant routing channel width.

Abstract: An improved Phase Locked Loop (PLL) for digital integrated circuits. A characteristic of this PLL is that the Voltage Controlled Oscillator (VCO) output is fed to the phase and frequency detector (PFD) input through a clock-tree replica providing a delay equal to the routed clock tree. “This enables the PLL to maintain the proper phase even during a sleep mode of operation.

Abstract: A differential input receiver with hysteresis on both sides of the reference voltage may include a two-input, one-output differential amplifier including two input transistors having a common terminal connected together. The control terminal of each transistor may be connected to one of the inputs of the differential amplifier. The output of the differential amplifier may be connected to a set of cascaded digital inverters/buffers, and an output of each digital buffer may be connected to the control terminal of a feedback transistor. The feedback transistor may be connected in parallel across each of the input transistors so that when one input voltage increases above or decreases below the input voltage at the second input by a predetermined threshold value, the feedback transistors operate to provide positive feedback to facilitate a rapid switching action at the output.

Abstract: An electronic circuit containing one or more digital synchronous sequential logic blocks at least one of which is either selected or deselected during operation. The electronic circuit includes an improved clock distribution scheme that reduces power consumption, comprising identifying means for determining the select/deselect state of each said deselectable synchronous sequential logic block, coupled to disabling means for disabling the clock input to each deselected synchronous sequential logic block.

Abstract: A Programmable Logic Device (PLD) incorporating a plurality of Programmable Logic Blocks (PLBs) providing enhanced flexibility for Cascade logic functions, each comprising a multi-input Look Up Table (LUT) providing one input to a Cascade Logic block for implementing desired Cascade Logic functions. The other input of the Cascade Logic block is a Cascade-In signal. A 2-input selection multiplexer receives one input from the output of the Cascade Logic block and the other from the output of the LUT for selecting either the Cascade Logic output or the LUT output as the unregistered output. The arrangement is such that the Cascade output and the multiplexer output are simultaneously available from the PLB.

Abstract: A digital clock modulator provides a smoothly modulated clock period to reduce emitted electro-magnetic radiation (EMR). The digital clock modulator includes a plurality of delay elements connected in series and receiving as an input an unmodulated clock signal. A multiplexer receives inputs from unequally spaced taps between the delay elements. A control block provides selection inputs to the multiplexer, and receives the unmodulated clock signal from the delay elements. The delay elements include a last delay element providing the unmodulated clock signal to the control block. The last delay element has a predetermined delay for ensuring that the delay elements and related signal paths are in a same stable state before control to the multiplexer changes.

Abstract: The present invention provides a Programmable Logic Device (PLD) incorporating a two-input multiplexer for providing a Cascade Logic output and having a Cascade Logic input coupled to a select line. A two-input multiplexer provides the desired configurable Cascade Logic function, and an initialization circuit sets the initial value for the Cascade logic under control of an initialization configuration bit. The multiplexer that provides the Cascade Logic output also provides the desired configurable Cascade Logic function using the Look-up table (LUT) and configuration bits.

Abstract: A method for reducing offset voltage in an operational amplifier without the need for switched-capacitors, includes introducing a tapped resistor chain between the common connected terminals of the transistors of the input differential pair of the operational amplifier and connecting the tail current source/sink of the differential amplifier to a selected tap of the resistor chain. The invention further provides an improved operational amplifier in accordance with the above method.

Abstract: The method for mapping a logic circuit to a plurality of interconnectable, programmable look up tables (LUT) elements includes forming logic element groups including individual logic elements and/or previously formed logic element groups that are capable of being accommodated within the fanin and/or fanout capacity of a target LUT. The method further includes mapping the formed logic element group to the target LUT, and repeating the process for forming logic element groups and mapping to target LUTs for the entire network in a manner such that at each stage only the unmapped logic element/elements and mapped logic element groups of the previous stage are considered for mapping.

Abstract: A CMOS output buffer uses feedback from a ground node to reduce ground bounce by utilizing a tolerable ground bounce limit, making it less sensitive to operating conditions and processing parameters. An input to the NMOS device of the output buffer is provided by the output of a control element which receives a first input from a pre-driver and a second input (i.e., the feedback) from the ground node.

Abstract: An improved phase locked loop (PLL) includes a frequency multiplier and a voltage controlled oscillator (VCO). The VCO includes a control circuit for automatically adjusting its initial free-running frequency in response to changes in an integer divider value. The adjusting is done so that the frequency difference between the initial free-running frequency divided by the integer divider value and a reference frequency is maintained at an approximately constant value. This results in a controllable lock time that is independent of the integer divider value.

Abstract: A programmable output buffer providing variable drive strength and slew rate for a given noise limit that includes a driver stage that generates the output of the buffer and a plurality of selectively enabled switching elements, at least a predriver stage providing a plurality of selectable switching elements that enables the selected drive stage switching elements, and a selection means that enables the required predriver switching elements in the desired sequence to provide the desired drive strength and slew rate.