Abstract: A circuit including an initiator of a transaction, an interconnect, and a controller. The controller is configured in response to a condition in a least one first part of the circuit to send a notification via the interconnect to at least one block in a second part of the circuit. The notification includes information about the condition in the first part of the circuit, the condition preventing a response to the transaction from being received by the initiator.

Abstract: A first arrangement including an interface configured to receive transactions with an address from a second arrangement having a first memory space; a translator configured to translate an address of a first type of received transaction to a second memory space of the first arrangement, the second memory space being different to the first memory space; and boot logic configured to map a boot transaction of the received transactions to a boot region in the second memory space.

Abstract: A cache memory controller including: a pre-fetch requester configured to issue pre-fetch requests, each pre-fetch request having one of a plurality of different quality of services.

Abstract: A first arrangement including a first interface configured to receive a memory transaction having an address from a second arrangement; a second interface; an address translator configured to determine based on said address if said transaction is for said first arrangement and if so to translate said address or if said transaction is for a third arrangement to forward said transaction without modification to said address to said second interface, said second interface being configured to transmit said transaction, without modification to said address, to said third arrangement.

Abstract: A first cache arrangement including an input configured to receive a memory request from a second cache arrangement; a first cache memory for storing data; an output configured to provide a response to the memory request for the second cache arrangement; and a first cache controller; the first cache controller configured such that for the response to the memory request output by the output, the cache memory includes no allocation for data associated with the memory request.

Abstract: A package includes a die and at least one further die. The die has an interface configured to receive a transaction request from the further die via an interconnect and to transmit a response to the transaction request to said further die via the interconnect. The die also has mapping circuitry which is configured to allocate to the received transaction a local source identity information as source identity information, the local source identity information comprising one of a set of reusable local source identity information. This ensures the order of transactions tagged with a same original source identity and target and allows transactions tagged with different source identifiers to be processed out of order.

Abstract: An image sensor has a per-column ADC arrangement including first and second capacitors allowing a comparator circuit to perform correlated double sampling. The capacitors are continuously connected to, respectively, the analog pixel signal and a ramp signal without use of a hold operation. The comparator circuit comprises a differential input being connected to the junction of the two capacitors and being biased by a reference signal. The reference signal is preferably sampled and held from a reference voltage. The use of a differential input as first stage of the comparator addresses problems arising from ground voltage bounce when a large pixel array images a scene with low contrast. Connectivity of the differential input stage allows the ramp signal to see a constant capacitive load thus reduce image artifacts referred to as smear.

Abstract: An imaging system includes a plurality of pixels. A pixel readout circuit produces a plurality of first image frames from those pixels. An image output circuit produces a plurality of second image frames and operates to produce a second image frame from more than one of the first image frames. The pixel readout circuit is enabled to produce the first images frames at a rate faster than the image output circuit produces the second image frames. Through combining first image frames, by averaging or other statistical combinations, the photon shot noise of second image frames is reduced. Photon shot noise affects images with high light levels more than those with low light levels and, as such, the system processing alters the rate of first image frames dependent on the current light levels.

Abstract: A system including input circuitry for receiving from one of a plurality of sources at least one packet stream including a plurality of packets for providing audio, video, private data and/or associated information; at least one output for outputting at least one packet of the at least one packet stream to circuitry arranged to provide an output stream; wherein the system is arranged to provide a tag indicative of the source, the tag being associated with the at least one packet.

Abstract: A processor and a method for executing VLIW instructions by first fetching a VLIW instruction and then identifying from option bits encoded in a first one of the instructions within the fetched VLIW instruction packet which, if any, of the remaining instructions within the VLIW instruction are to be executed in the same execution cycle as the first instruction. Finally, executing the first instruction and any remaining instructions identified from the encoded option bits.

Abstract: A method of designing a clock distribution network in an integrated circuit, the method including: creating a clock distribution network with all cells having a maximum drive strength; supplying parameters of the clock distribution network to a timing analysis tool; in the timing analysis tool, analyzing the timing of the clock distribution network in an iterative process including manipulating the drive strength of at least one cell in the clock distribution network and assessing whether there is an improvement in the timing, wherein the iterative process ceases where there is no improvement in the timing; and outputting a list of cells for which the drive strength was changed.

Abstract: A processor and a method for executing VLIW instructions using pipeline execution wherein each VLIW instruction includes a plurality of instructions and wherein the pipeline includes at least the following stages: first and second instruction fetch stages, a pre-decode stage, an instruction dispatch stage, first and second decoding stages, an execution stage and a write-back stage. During the first instruction fetch stage the number of outstanding instructions is determined where these outstanding instructions are from previous VLIW instructions that have not yet been issued for execution. During the second instruction fetch stage a comparison is performed on whether the number of outstanding instructions is less then the number of instructions in a VLIW instruction where if the number of outstanding instructions is less than the number of instructions in an instruction packet then the next VLIW instruction is fetched and the outstanding instructions are shifted and aligned with the fetched VLIW instruction.

Abstract: An FFT/IFFT processor having computation logic capable of processing butterfly operations, and storage for storing the operands of butterfly operations, including a mechanism for storing the operands of multiple consecutive butterfly operations in contiguous storage locations and wherein the computation logic is capable of simultaneously accessing and processing said multiple butterfly operations.

Abstract: A processing system for accessing first and second data types. The first data type is data supplied from a peripheral and the second data type is randomly accessible data held in a data memory. The processing system includes: a processor for executing instructions; a stream register unit connected to supply data from the peripheral to the processor; and a FIFO. The FIFO is connected to receive data from the peripheral and connected to the stream register unit by a communication path, along which the received data can be supplied from the FIFO to the stream register unit. The Processing system also includes a memory bus connected between the data memory and the processor, across which the processor can access the randomly accessible data.

Abstract: An arrangement of arithmetic logic units carries out an operation on at least one operand, wherein the operation is determined by operation codes received by the arithmetic logic units. The operation codes and at least one operand are received on a first clock cycle. The result of the operation is output from at least one arithmetic logic unit to at least one further arithmetic logic unit. A result of the plurality of arithmetic logic units is then output on a next clock cycle.

Abstract: There is disclosed a method of helping mobile stations such as voice over IP devices to roam between wireless access points, by each access point transmitting the MAC address of a spanning tree algorithm root switch of the local network domain. This MAC address is used by mobile stations to detect if two access points are in a common network domain.

Abstract: A memory access system including a memory in which data is organized in pages, each page holding a sequence of data elements; means for receiving a requested address including a requested page address and a requested data element address; logic for accessing a current page from the memory using a current page address; logic for reading out data elements of the current page in the sequence in which they are held in memory; logic for comparing the requested page address with the current page address and for issuing a memory access request with the requested page address when they are not the same; and logic operable when the requested page address is the same as the current page address for comparing a requested data element address with the current address of a data element being read out and returning the data element when the requested data element address matches the current data element address.

Abstract: A semiconductor packaging unit mounts onto a board by solder joints. The unit includes, disposed along one axis, a semiconductor component having on a rear face protruding electrical connection lugs designed to be soldered onto the board and an external cage surrounding the component and having a rear edge designed to be soldered onto the board and a front part through which a front part of the component passes. The component and the cage are designed to axially slide with respect to one another in such a manner as to be brought into their soldering position with respect to the board and having complementary holding parts coming into contact and designed to hold them with respect to one another when they are axially removed from the soldering position and to free them with respect to one another when they are at the soldering position.

Abstract: A semiconductor packaging unit mounts onto a board by solder joints. The unit includes, disposed along one axis, a semiconductor component having on a rear face protruding electrical connection lugs designed to be soldered onto the board and an external cage surrounding the component and having a rear edge designed to be soldered onto the board and a front part through which a front part of the component passes. The component and the cage are designed to axially slide with respect to one another in such a manner as to be brought into their soldering position with respect to the board and having complementary holding parts coming into contact and designed to hold them with respect to one another when they are axially removed from the soldering position and to free them with respect to one another when they are at the soldering position.