Abstract: A bandgap reference voltage generator includes a bipolar assembly having a first resistor, a first branch and a second branch that is in parallel with the first branch. The first branch includes a first bipolar transistor with a base coupled to a fixed voltage. The second branch includes a second bipolar transistor with a base coupled to the fixed voltage and a second resistor coupled in series with the second bipolar transistor. A differential module is coupled to the first and second bipolar transistors and configured to balance the currents in the first and the second branches. The bandgap reference voltage is output at a node to which the first resistor is connected.

Abstract: A method for recovering a clock frequency of a CAN bus, the method including: receiving a data signal, wherein the data signal includes at least one state transition; detecting the state transition; and adjusting a frequency of a clocking signal generated by an oscillator circuit, wherein the frequency is adjusted when the state transition is detected and adjusting the frequency is for recovering the clock frequency of the CAN bus.

Abstract: In one embodiment, a method for converting an analog input value to a digital output value is disclosed. A successive approximation is performed. The analog input is quantized to a first quantized value, which is converted to a first analog value using a DAC. The first analog value is subtracted from the analog input value to form a first residue. The first residue is quantized to form a second quantized value, and a second residue is formed by converting the second quantized value to a second analog value using the DAC and subtracting the second analog value from the first residue value. The second residue is then quantized to form a third quantized value. The first, second and third quantized values are converted into a digital output value. The first, second and third quantized values each have at least three levels.

Abstract: A pass gate circuit includes a first transistor coupled between an input node (receiving an input signal) and an output node (outputting an output signal). A second transistor is configured to generate a voltage difference in response to a bias current flowing therethrough, wherein that voltage difference is applied between a first gate of the first transistor and the output node. A differential amplifier functions to compare the voltage at the output node to a reference voltage and generate the bias current in response to that comparison.

Abstract: The gate of a drive transistor having a drain and source is discharged by a circuit including a sensing circuit configured to sense a drain-to-source voltage of the drive transistor. A first current sink path is coupled to the gate of the drive transistor. The first current sink path applies a high discharge current to the gate of the drive transistor when the sensing current senses a lower drain-to-source voltage of the drive transistor. A second current sink path is also coupled to the gate of the drive transistor. The second current sink path is configured to apply a low discharge current to the gate of the drive transistor when the sensing current senses a higher drain-to-source voltage of the drive transistor.

Abstract: Circuits and methods to realize a power-efficient high frequency buffer. The amplitude of a buffered signal is detected and compared with the amplitude of the input signal. The comparison result can be fed back to the digitally-controlled buffer to keep the output gain constant. By using feedback control, the buffer can be kept at the most suitable biasing condition even if the load condition or signal frequency varies.

Abstract: A level shifting circuit includes a current mirror that generates a first bias current and a second bias current (proportional to the first bias current with a first ratio). A first level shifter is coupled between a first input node (receiving a first input signal) and a first output node coupled to an input of the current mirror. The first level shifter applies a first voltage variation to the first input signal in response to the first bias current. A second level is coupled between a second input node (receiving a second input signal) and a second output node coupled to an output of the current mirror. The second level shifter applies a second voltage variation (associated with the first voltage variation) to the second input signal in response to the second bias current.

Abstract: A circuit includes a charge pump, a first level shifter, a second level shifter, a voltage follower and a current mirror. The charge pump is configured to generate a voltage difference between the input node and the output node. The first level shifter is coupled to the charge pump output and configured to apply a first voltage variation to the charge pump output in response to a bias current. The second level shifter is coupled to the input node and configured to apply a second voltage variation to the charge pump input. The voltage follower is configured to equalize outputs from the first and second level shifters and provide a difference current which is multiplied by the current multiplier to generate a charging current applied to the charge pump.

Abstract: The gate of a drive transistor having a drain and source is discharged by a circuit including a sensing circuit configured to sense a drain-to-source voltage of the drive transistor. A first current sink path is coupled to the gate of the drive transistor. The first current sink path applies a high discharge current to the gate of the drive transistor when the sensing current senses a lower drain-to-source voltage of the drive transistor. A second current sink path is also coupled to the gate of the drive transistor. The second current sink path is configured to apply a low discharge current to the gate of the drive transistor when the sensing current senses a higher drain-to-source voltage of the drive transistor.

Abstract: A Local Interconnect Network (LIN) driver circuit employs a charging/discharging current applied to the gate of a driver transistor coupled to an LIN bus. The charging current includes a constant charging current and an additional soft charging current, whereas the discharging current includes a constant discharging current and an additional soft discharging current. As a result of the soft charge/discharge components, there is a significant reduction in electromagnetic emission on the LIN bus.

Abstract: The present invention provides a technical solution for a unified driver used in a handheld device. An embodiment of the technical solution may comprise a unified driving method used in a handheld device, which method may comprise: determining driver types of currently installed hardware; setting a current dispatch table on the basis of the driver type and a unified dispatch table suitable for multiple hardware and driving corresponding hardware or software by calling the current dispatch table.

Abstract: A linear voltage regulator includes a Miller frequency compensation having a movable zero, which tracks the frequency of the load pole as the load condition changes. The compensated voltage regulator maintains stability under variable load conditions. Because of the Miller effect, DC open-loop gain and bandwidth are not sacrificed for stability. The compensated voltage regulator can therefore maintain high power supply rejection ratio (PSRR).

Abstract: A pass gate circuit includes a first transistor coupled between an input node (receiving an input signal) and an output node (outputting an output signal). A second transistor is configured to generate a voltage difference in response to a bias current flowing therethrough, wherein that voltage difference is applied between a first gate of the first transistor and the output node. A differential amplifier functions to compare the voltage at the output node to a reference voltage and generate the bias current in response to that comparison.

Abstract: The present invention provides a technical solution for a unified driver used in a handheld device. An embodiment of the technical solution may comprise a unified driving method used in a handheld device, which method may comprise: determining driver types of currently installed hardware; setting a current dispatch table on the basis of the driver type and a unified dispatch table suitable for multiple hardware and driving corresponding hardware or software by calling the current dispatch table.

Abstract: A drive circuit includes a switching transistor having a design maximum voltage V2 and a cascode transistor having a design maximum voltage V1, wherein the cascode transistor is source-drain coupled in series with the switching transistor. The circuit further includes a current source coupled between an intermediate voltage node and a gate of the cascode transistor. If the drive circuit is a low side driver, the intermediate voltage node receives an intermediate voltage Vmed set below a high supply voltage Vhigh and that meets the following conditions: a) Vmed<=V2 and b) Vhigh?Vmed<=V1. If the drive circuit is a high side driver, the intermediate voltage node receives an intermediate voltage Vmed set below the high supply voltage and that mees the following conditions: a) Vmed<=V1 and b) Vhigh?Vmed<=V2. The circuit may be configured as a push pull driver by coupling a high side driver and low side driver in series.

Abstract: The present invention provides a technical solution for a unified driver used in a handheld device. An embodiment of the technical solution may comprise a unified driving method used in a handheld device, which method may comprise: determining driver types of currently installed hardware; setting a current dispatch table on the basis of the driver type and a unified dispatch table suitable for multiple hardware and driving corresponding hardware or software by calling the current dispatch table.

Abstract: In one embodiment, a system for providing short circuit protection is disclosed. The system has a supply circuit and a series switch. The supply circuit has a supply input and a supply output, and is configured to deliver an output current at the supply output, and to disable the supply output if the output current exceeds a first current limit. The series switch coupled between the supply output of the supply circuit and a supply node, and the supply node is configured to be coupled to a load.

Abstract: A bandgap reference voltage generator includes a bipolar assembly having a first resistor, a first branch and a second branch that is in parallel with the first branch. The first branch includes a first bipolar transistor with a base coupled to a fixed voltage. The second branch includes a second bipolar transistor with a base coupled to the fixed voltage and a second resistor coupled in series with the second bipolar transistor. A differential module is coupled to the first and second bipolar transistors and configured to balance the currents in the first and the second branches. The bandgap reference voltage is output at a node to which the first resistor is connected.

Abstract: In one embodiment, a method for converting an analog input value to a digital output value is disclosed. A successive approximation is performed. The analog input is quantized to a first quantized value, which is converted to a first analog value using a DAC. The first analog value is subtracted from the analog input value to form a first residue. The first residue is quantized to form a second quantized value, and a second residue is formed by converting the second quantized value to a second analog value using the DAC and subtracting the second analog value from the first residue value. The second residue is then quantized to form a third quantized value. The first, second and third quantized values are converted into a digital output value. The first, second and third quantized values each have at least three levels.

Abstract: In one embodiment, a system for controlling a motor is disclosed. The system has a driver circuit configured to drive a motor, a current sensing impedance coupled to the driver circuit, and an overload detection circuit coupled to the current sending impedance that has a transistor and a detection output node.