Abstract: In one embodiment, a method for converting an analog input value to a digital output value is disclosed. A successive approximation is performed. The analog input is quantized to a first quantized value, which is converted to a first analog value using a DAC. The first analog value is subtracted from the analog input value to form a first residue. The first residue is quantized to form a second quantized value, and a second residue is formed by converting the second quantized value to a second analog value using the DAC and subtracting the second analog value from the first residue value. The second residue is then quantized to form a third quantized value. The first, second and third quantized values are converted into a digital output value. The first, second and third quantized values each have at least three levels.

Abstract: Circuits and methods to realize a power-efficient high frequency buffer. The amplitude of a buffered signal is detected and compared with the amplitude of the input signal. The comparison result can be fed back to the digitally-controlled buffer to keep the output gain constant. By using feedback control, the buffer can be kept at the most suitable biasing condition even if the load condition or signal frequency varies.

Abstract: A method for recovering a clock frequency of a CAN bus, the method including: receiving a data signal, wherein the data signal includes at least one state transition; detecting the state transition; and adjusting a frequency of a clocking signal generated by an oscillator circuit, wherein the frequency is adjusted when the state transition is detected and adjusting the frequency is for recovering the clock frequency of the CAN bus.

Abstract: A fully integrated ramp generator circuit includes a first current generator that sources current to first capacitor through a first transistor that is gate controlled by the complement of a periodic signal. The ramping voltage stored on the first capacitor is buffered to an output node as a ramp output signal. A second transistor couples the output node to the first current generator and is gate controlled by the periodic signal. The periodic signal is generated at the output of a flip-flop that receives an input clock signal and reset signal. The reset signal is generated by a comparator circuit operable to compare the voltage on a second capacitor to a reference. The second capacitor is charged by a second current source and discharged by a third transistor that is gate controlled by the periodic signal.

Abstract: A drive circuit includes a switching transistor having a design maximum voltage V2 and a cascode transistor having a design maximum voltage V1, wherein the cascode transistor is source-drain coupled in series with the switching transistor. The circuit further includes a current source coupled between an intermediate voltage node and a gate of the cascode transistor. If the drive circuit is a low side driver, the intermediate voltage node receives an intermediate voltage Vmed set below a high supply voltage Vhigh and that meets the following conditions: a) Vmed<=V2 and b) Vhigh?Vmed<=V1. If the drive circuit is a high side driver, the intermediate voltage node receives an intermediate voltage Vmed set below the high supply voltage and that mees the following conditions: a) Vmed<=V1 and b) Vhigh?Vmed<=V2. The circuit may be configured as a push pull driver by coupling a high side driver and low side driver in series.

Abstract: In one embodiment, a method for converting an analog input value to a digital output value is disclosed. A successive approximation is performed. The analog input is quantized to a first quantized value, which is converted to a first analog value using a DAC. The first analog value is subtracted from the analog input value to form a first residue. The first residue is quantized to form a second quantized value, and a second residue is formed by converting the second quantized value to a second analog value using the DAC and subtracting the second analog value from the first residue value. The second residue is then quantized to form a third quantized value. The first, second and third quantized values are converted into a digital output value. The first, second and third quantized values each have at least three levels.

Abstract: A buffer circuit includes a biasing circuit operable to generate first and second biasing signals. A capacitive network includes an input adapted to receive an input signal and the capacitive network is operable responsive to the input signal to generate first and second bootstrapped signals. A push-pull stage includes first and second control inputs and an output. The push-pull stage is coupled to the biasing circuit to receive the first and second biasing signals on the first and second control inputs, respectively, and is coupled to the capacitive network to receive the first and second bootstrapped signals on the first and second control inputs, respectively. The push-pull stage is operable to generate a buffered output signal on the output responsive to the first and second bootstrapped signals.

Abstract: For coarse resistor string DACs, a resistor string is placed in an array of columns and rows, each resistor tap is connected to a switch network, and a decoder is used to select switches to be closed such that sub-DAC voltage comes from the resistor taps connected to the selected switches. The voltages from each row are fed into multiplexers, wherein the multiplexers produce output voltages. DAC circuit designs extend the resolution of the output voltages by feeding them into a voltage interpolation amplifier. A method and apparatus are disclosed for implementing Gray code to design coarse DAC architecture for voltage interpolation such that the number of switches required by the circuit is significantly reduced, thereby decreasing required surface area, and improving glitch performance without increasing design complexity.

Abstract: For voltage interpolation amplifiers used in digital-to-analog converter architecture, the number of input differential pairs required by the voltage interpolation amplifier may be reduced such that an N-bit voltage interpolation amplifier comprises N+1 input differential pairs connected through a resistor attenuation network to provide a binary-weighted effective transconductance. In comparison to conventional voltage interpolation amplifier designs, the number of input differential pairs and power consumed by the circuit is significantly reduced, thereby creating a more area- and power-efficient voltage interpolation amplifier.

Abstract: For high resolution resistor string DACs, a resistor string is placed in an array of columns and rows, each resistor tap is connected to a switch network, and a decoder is used to select switches to be closed such that sub-DAC voltage comes from the resistor taps connected to the selected switches. The voltages from each row of the resistor string are fed into a multiplexer, wherein the multiplexer produces an output voltage. A method and apparatus are disclosed for implementing the reflective nature of Gray code to design a DAC such that all the switches in a column of the resistor string may be controlled with only one control signal, thereby reducing extra routing costs, surface area, and dynamic power consumed by the circuit.

Abstract: An embodiment of a circuit for driving an under-damped system comprises first and second signal generators. The first generator is operable to generate a first drive signal. And the second generator is operable to receive the first drive signal and a second drive signal, and to generate from the first and second drive signals a system drive signal having a first amplitude for a first duration and having a second amplitude after the first duration, the system drive signal operable to cause the under-damped system to operate in a substantially damped manner. Either or both of the first and second generators may be programmable such that one may adjust the response of any under-damped system by generating an appropriate drive signal instead of by physically modifying the system itself.

Abstract: In one embodiment, a system for controlling a motor is disclosed. The system has a driver circuit configured to drive a motor, a current sensing impedance coupled to the driver circuit, and an overload detection circuit coupled to the current sending impedance that has a transistor and a detection output node.

Abstract: In one embodiment, a system for providing short circuit protection is disclosed. The system has a supply circuit and a series switch. The supply circuit has a supply input and a supply output, and is configured to deliver an output current at the supply output, and to disable the supply output if the output current exceeds a first current limit. The series switch coupled between the supply output of the supply circuit and a supply node, and the supply node is configured to be coupled to a load.

Abstract: A linear voltage regulator includes a Miller frequency compensation having a movable zero, which tracks the frequency of the load pole as the load condition changes. The compensated voltage regulator maintains stability under variable load conditions. Because of the Miller effect, DC open-loop gain and bandwidth are not sacrificed for stability. The compensated voltage regulator can therefore maintain high power supply rejection ratio (PSRR).

Abstract: The present invention provides a technical solution for a unified driver used in a handheld device. An embodiment of the technical solution may comprise a unified driving method used in a handheld device, which method may comprise: determining driver types of currently installed hardware; setting a current dispatch table on the basis of the driver type and a unified dispatch table suitable for multiple hardware and driving corresponding hardware or software by calling the current dispatch table.

Abstract: A buffer circuit includes a biasing circuit operable to generate first and second biasing signals. A capacitive network includes an input adapted to receive an input signal and the capacitive network is operable responsive to the input signal to generate first and second bootstrapped signals. A push-pull stage includes first and second control inputs and an output. The push-pull stage is coupled to the biasing circuit to receive the first and second biasing signals on the first and second control inputs, respectively, and is coupled to the capacitive network to receive the first and second bootstrapped signals on the first and second control inputs, respectively. The push-pull stage is operable to generate a buffered output signal on the output responsive to the first and second bootstrapped signals.

Abstract: A calibrator circuit and method for VCOM voltage adjustment for an LCD includes using integrated programmable resistive arrays. The method uses two DACs and three integrated circuit arrays to provide all of the advantages of VCOM calibrator circuits using external resistive voltage-dividers. The integrated circuit resistor arrays reduce the number of external components and PCB space. The method used is suitable for higher resolution adjustment of the VCOM voltage and no calculation is required in the whole adjustment procedure, which saves labor cost, time and enables automation of the calibrator fabrication.

Abstract: A calibrator circuit and method for VCOM voltage adjustment for an LCD includes using integrated programmable resistive arrays. The method uses two DACs and three integrated circuit arrays to provide all of the advantages of VCOM calibrator circuits using external resistive voltage-dividers. The integrated circuit resistor arrays reduce the number of external components and PCB space. The method used is suitable for higher resolution adjustment of the VCOM voltage and no calculation is required in the whole adjustment procedure, which saves labor cost, time and enables automation of the calibrator fabrication.

Abstract: Due to the lack of 3D applications based on the OpenGL|ES standard, a desire exists to run 3D applications based on the OpenGL standard on OpenGL|ES mobile devices such as cellular telephones. To address this desire, one must be able to translate function calls between OpenGL and OpenGL|ES. In supporting this translation, and so as to ensure proper data state for the continued execution of the OpenGL application, global GL states which might be changed by an OpenGL|ES function used during translation are stored. The OpenGL to OpenGL|ES translation is then effectuated by substituting appropriate OpenGL|ES commands for OpenGL commands, and passing OpenGL|ES APIs for OpenGL|ES implementation. Thereafter, the global GL states which were previously saved are restored such that the performed translation does not adversely impact continued execution of the OpenGL configured application.