Abstract: An encapsulation hood is fastened onto electrically conductive zones of a support substrate using springs. Each spring has a region in contact with an electrically conductive path contained in the encapsulation hood and another region in contact with a corresponding one of the electrically conductive zones. The fastening of the part of the encapsulation hood onto the support substrate compresses the springs and further utilizes a bead of insulating glue located between the compressed springs.

Abstract: Cantilever probes are produced for use in a test apparatus of integrated electronic circuits. The probes are configured to contact corresponding terminals of the electronic circuits to be tested during a test operation. The probe bodies are formed of electrically conductive materials. On a lower portion of each probe body that, in use, is directed to the respective terminal to be contacted, an electrically conductive contact region is formed having a first hardness value equal to or greater than 300 HV; each contact region and the respective probe body form the corresponding probe.

Abstract: A memory cell including a set of active regions that overlay a set of gate regions to form a pair of cross-coupled inverters. A first active region extends along a first axis. A first gate region extends transversely to the first active region and overlays the first active region to form a first transistor of the pair of cross-coupled inverters. A second gate region extends transversely to the first active region and overlays the first active region to form a second transistor of the pair of cross-coupled inverters. A second active region extends along a second axis and overlays the first gate region to form a third transistor of the pair of cross-coupled inverters. A fourth active region extending along a third axis and overlays a gate region to form a transistor of a read port.

Abstract: A structure including a base portion (e.g., made of a graphite-based or graphene-based material) with at least one surface that is coated with a homogenous coating layer (e.g., made of silicon-carbide (SiC)). The homogenous coating layer prevents contaminants (e.g., carbon) from being released by the base portion into a cavity of a processing tool when heated to process one or more workpieces (e.g., silicon substrate, silicon wafers, etc.) present within the cavity. The homogenous coating layer includes grains and grain boundaries that are relatively the same size and shape as each other, which further prevents propagation of defects (e.g., cracking, peeling, etc.) that could potentially cause exposure of a region of the first surface of the base portion to the cavity of the processing tool contaminating the one or more workpieces present within the cavity of the processing tool.

Abstract: A memory array includes a plurality of bit-cells arranged as a set of rows of bit-cells intersecting a plurality of columns. The memory array also includes a plurality of in-memory-compute (IMC) cells arranged as a set of rows of IMC cells intersecting the plurality of columns of the memory array. Each of the IMC cells of the memory array includes a first bit-cell having a latch, a write-bit line and a complementary write-bit line, and a second bit-cell having a latch, a write-bit line and a complementary write-bit line, wherein the write-bit line of the first bit-cell is coupled to the complementary write-bit line of the second bit-cell and the complementary write-bit line of the first bit-cell is coupled to the write-bit line of the second bit-cell.

Abstract: A sensor module includes a pattern generator configured to generate a variable frequency self-test signal. The sensor module includes an inertial sensor including a self-test electrode configured to receive the frequency sweep self-test signal. The inertial sensor is configured to generate an analog sensor signal based on the self-test signal. The sensor module includes an analog to digital converter configured to generate a digital sensor signal based on the analog sensor signal and a demodulator including a first input configured to receive the digital sensor signal, a second input configured to receive the self-test signal, and an output configured to output a demodulated signal. The sensor module includes a first low pass filter coupled to the output of the demodulator and configured to generate a baseband signal. The sensor module includes a calibration circuit configured to identify different MEMS characteristics, like resonance frequency, Q-factor, or sensitivity based on the baseband signal.

Abstract: An electrostatic discharge protection circuit protects a first transistor. The circuit includes N diodes in series between conduction terminals of the first transistor. A second transistor and third transistor are connected in series between the conduction terminals of the first transistor. A control terminal of the third transistor is coupled to an anode of the N diodes. A first inverter couples the control terminals of the first and second transistors. A fourth transistor is connected in parallel with the first transistor. A control terminal of the fourth transistor is coupled to the junction point of the second and third transistors. A capacitor is arranged between the control terminal of the fourth transistor and a conduction terminal of the first transistor.

Abstract: A memory array includes memory cells arranged in a matrix with cell rows coupled to word lines and cell columns coupled to output bit lines. A control circuit maps a first group of memory cells to a first in-memory compute operation producing computation output signals on first output bit lines from a first matrix vector multiplication of a first input vector with a first group of computation weights stored in the first group of memory cells and maps a second group of memory cells to a second in-memory compute operation producing computation output signals on second output bit lines, different from the first output bit lines, from a second matrix vector multiplication of a second input vector, different from the first input vector, with a second group of computation weights stored in the second group of memory cells. The first and second in-memory compute operations are substantially simultaneously executed.

Abstract: A substrate includes electrically conductive leads arranged laterally of a die mounting location. A semiconductor die is mounted at the die mounting location. An electrical coupling member electrically couples the semiconductor die with one or more electrically conductive leads. The electrical coupling member includes one or more electrically conductive pads having first and second electrically conductive ribbons protruding therefrom. The first and second electrically conductive ribbons have proximal ends at the electrically conductive pad and distal ends away from the electrically conductive pad. The distal ends of the first and second electrically conductive ribbons are electrically coupled to the semiconductor die and an electrically conductive lead, respectively, to provide electrical coupling therebetween.

Abstract: A method of operating an inertial sensor module includes receiving a stream of inertial sensor data representing activity of a user of an electronic device and generating a plurality of wavelet sub-bands by performing a wavelet transform on the inertial sensor data. The method includes identifying a wavelet sub-band of highest energy from the plurality of wavelet sub-bands, generating augmented inertial sensor data by combining the wavelet sub-band of highest energy to the inertial sensor data, and identifying a first transition in the activity of the user based on the augmented inertial sensor data.

Abstract: Disclosed herein is method for fault detection and communication in analog power electronic circuits with a multiplicity of electronic fuses (e.g., a primary fuse and at least one secondary fuse). Current flow is monitored through each fuse. Fault conditions in these electronic fuses are identified. Upon detection, the fault signaling line, which is common to all fuses, is driven to a voltage indicative of the detected fault condition. The primary electronic fuse then latches the voltage on this fault signaling line. A detection and communication circuit enables corrective actions to be performed at the fuse level, dictated by the latched voltage.

Abstract: An integrated circuit package includes a support plate having a mounting face. An electronic chip, having a rear face and a front face, is mounted on the mounting face with the front face electrically connected to the mounting face of the support plate. A deformable thermally conductive film covers at least one portion of the rear face of the electronic chip so that the film is in contact with the rear face.

Abstract: Composite material comprising a fluoropolymer matrix and a filler formed of nanoparticles of a ceramic of the BZT-?BXT type wherein X is selected from Ca, Sn, and Mn and a is a molar fraction selected in the range between 0.10-0.90 doped with at least one doping element selected from the group consisting of Nb, La, Mn, Nd and W, wherein when X is Mn, the doping element is not Mn, wherein said nanoparticles have an average diameter comprised between 10 and 25% by weight on the total weight of the composite. The composite material is used to form a thin film usable as a piezoelectric material with inductive properties in electronic components, for example acoustic sensors such as microphones, and energy harvesting transducers.

Abstract: Provided is a power converter including first, second, third and fourth nodes and a wire bonding test circuit. The wire bonding test circuit includes a multiplexer having a first terminal of a first side coupled to the first node and second and third terminals of a second side. The wire bonding test circuit includes a first switch having a first terminal coupled to the second terminal or the third terminal of the multiplexer and a second terminal coupled to the second node. The wire bonding test circuit includes a second switch having a first terminal coupled to the second terminal or the third terminal of the multiplexer and a second terminal coupled to the third node. The wire bonding test circuit includes a third switch having a first terminal coupled to the second terminal or the third terminal of the multiplexer and a second terminal coupled to the fourth node.

Abstract: A method of facilitating live feedback on code generation includes generating first source code based on user configuration, presenting the generated first source code in a live preview user interface, and obtaining a change to the user configuration. The method also includes, responsive to the obtaining of the first change: generating second source code based on the first change; computing differences between the second source code and the first source code; and presenting the second source code in the live preview user interface by: visually signaling a correspondence between the first change and portions of the second source code that are associated with the differences; and visually distinguishing the portions of the second source code from other portions of the second source code.

Abstract: The bandwidth of SOC interfaces is exploited while minimizing the number of physical ports via a networking accelerator for use on board a vehicle, for instance, that comprises: media access control (MAC) controller circuitry configured to provide a MAC port layer to control exchange of information, wherein the exchange of information comprises data flow transmission to virtual machine ports (VMPs) over a data link; virtual machine transmission (VM Tx) bridge circuitry configured to handle transmission data flow to the VMPs; transmission router/switch circuitry configured to route/switch data flow from the MAC controller circuitry to the VM Tx bridge circuitry; and queue handler circuitry configured to provide queue management for data flow between the MAC controller circuitry and the VM Tx bridge circuitry.

Abstract: Provided is a module for monitoring instructions of a microcontroller. The module is adapted to receive instructions that are received at an input terminal of the microcontroller or that are being processed by a code pointer of the microcontroller. The module verifies the instructions received on the input terminal of the microcontroller or that are being processed by the code pointer of the microcontroller.

Abstract: An amplification circuit includes an amplifier circuit (provided by an operational amplifier) that amplifies a signal to be demodulated. A feedback loop of the amplification circuit has a resistance value that is controlled to discretely vary according to a level of an output node of the amplifier circuit. A comparison of the output level with respect to one or a plurality of thresholds, which define out-of-saturation operating ranges of the amplifier circuit, drives selection of the resistance value.

Abstract: The present description relates to a vertical power component formed in and on a semiconductor substrate doped with a first conductivity type and coated, on the upper side thereof, with a semiconductor layer doped with the first conductivity type. The component includes: an active region (100A); and first and second groups of first concentric field limiting rings surrounding the active region. Each first ring includes a first semiconductor region doped with a second conductivity type, opposite to the first conductivity type, extending vertically into the thickness of the semiconductor layer from the upper side thereof; and a second field limiting ring laterally interposed between the first and second groups of first field limiting rings (GR). The second ring includes a second doped semiconductor region of the second conductivity type extending vertically into the thickness of the semiconductor layer from the upper face thereof.

Abstract: A power circuit includes a power transistor coupled between input and output nodes and receiving a control signal. A current sensing current senses a power current provided by the power transistor to the output node and generates a sense voltage. A voltage sensing circuit senses a drain-to-source voltage of the power transistor and generates a VDS sense current. A safe operating area (SOA) shaping circuit has a gain set by an adjustable resistance that is dynamically adjusted based upon the VDS sense current, the SOA shaping circuit applying the gain to the sense voltage to produce an adjusted sense voltage. A timing circuit generates an intermediate voltage by comparing the adjusted sense voltage and a first reference. An output comparator asserts a flag in response to the intermediate voltage becoming at least equal to a second reference. The control signal is modified in response to assertion of the flag.