Abstract: A multiplexer includes an input, an output, and a main switch configured to pass a signal from the input to the output. The multiplexer includes two bootstrap circuits that collectively maintain a constant voltage between terminals of the main switch during alternating phases.

Abstract: A MEMS (MicroElectroMechanical System) device includes: a supporting body; a movable mass, constrained to the supporting body by flexures so as to be able to oscillate in a main direction; an actuator device, configured to apply to the movable mass an electrostatic actuation force, transverse to the main direction; and a control circuit configured to detect stiction conditions, in which the movable mass is stuck to the supporting body by a stiction force, and for driving the actuator device in response to recognition of the stiction conditions. The actuation force is a variable force with an actuation frequency band containing at least one resonance frequency in a direction transverse to the main direction of a mechanical system comprising the movable mass stuck to the supporting body.

Abstract: An in-memory computation device receives an input signal and provides an output signal. The device includes a memory array with memory cells coupled to word lines that receive word line activation signals indicative of the input signal and coupled to bit lines that generate bit line currents; and a digital detector for sampling the bit line current and, in response, providing the output signal. A digital detector includes: a control stage that compares the bit line current with at least one reference current and generates corresponding control signals; a selection stage that generates a total selection current based on the first bit line current and on the control signals; an integration stage that samples the total selection current; and a charge counter stage that generates the output signal on the basis of a sampled first total selection current and the control signals.

Abstract: An integrated circuit device includes: a Buck converter; and a control circuit for the Buck converter, which includes: a comparator configured to compare a feedback voltage of the Buck converter with a reference voltage that increases from a first voltage to a second voltage; a pulse-width modulator configured to generate a pulse-width modulated (PWM) signal having a timing-varying pulse width proportional to the reference voltage; an AND gate configured to generate a first control signal by performing a logic AND operation on an output of the comparator and the PWM signal; a pulse generator configured to generate a second control signal by generating a pulse in response to a rising edge in the output of the comparator; and a selection circuit configured to, based on an output voltage of the Buck converter, select the first control signal or the second control signal as a control signal for the Buck converter.

Abstract: An image acquisition device includes an array of color filters and an array of microlenses over the array of color filters. At least one layer made from an inorganic dielectric material is formed between the array of color filters and the array of microlenses.

Abstract: A control circuit and method, wherein an error signal is generated representative of a difference between an output voltage of a switching circuit and a nominal signal; a single control signal is generated, representative of an average error of the error signal; the single control signal is compared with a first periodic reference signal and a second periodic reference signal; a first pulse width modulated signal is generated by a Buck modulator; and a second pulse width modulated signal is generated by a Boost modulator. The maximum value of the first periodic reference signal and the minimum value of the second periodic reference signal are higher and lower, respectively, than the single control signal in a transient control mode between a Buck control mode and a Boost control mode.

Abstract: An HEMT transistor includes a semiconductor body having a semiconductive heterostructure. A gate region, of conductive material, is arranged above and in contact with the semiconductor body. A first insulating layer extends over the semiconductor body, laterally to the conductive gate region. A second insulating layer extends over the first insulating layer and the gate region. A first field plate region, of conductive material, extends between the first and the second insulating layers, laterally spaced from the conductive gate region along a first direction. A second field plate region, of conductive material, extends over the second insulating layer, and the second field plate region overlies and is vertically aligned with the first field plate region.

Abstract: A method of testing a photonic device includes providing a plurality of optical test signals at respective inputs of a first plurality of inputs of an optical input circuit located on a substrate, combining the plurality of optical test signals into a combined optical test signal at an output of the optical input circuit, transmitting the combined optical test signal through the output to an input waveguide of an optical device under test, the optical device under test being located on the substrate, and measuring a response of the optical device under test to the combined optical test signal. Each of the plurality of optical test signals comprises a respective dominant wavelength of a plurality of dominant wavelengths.

Abstract: In accordance with an embodiment, a system includes a phase-locked loop (PLL) configured to provide a first local oscillator (LO) signal and a voltage-controlled oscillator (VCO) signal; a first quadrature demodulator configured to downconvert global navigation satellite system signals to produce a first intermediate frequency (IF) signal; a first signal processing chain configured to pass the first IF signal; a second signal processing chain comprising a first frequency divider configured to produce a second LO signal based on the first LO signal, and a second quadrature demodulator configured to convert the first IF signal to a second IF signal using the second LO signal; and a third signal processing chain comprising a second frequency divider configured to produce a third LO signal based on the VCO signal, and a third quadrature demodulator configured to convert the first IF signal to a third IF signal using the third LO signal.

Abstract: A system including an asynchronous finite state machine that transitions from a first state to a second state in response to receiving a virtual-clock event signal. The system further includes a trigger circuit that asserts a trigger signal when a first-state asynchronous event signal is asserted while the asynchronous finite state machine is in the first state. The system further including a virtual clock-pulse circuit configured to generate the virtual-clock event signal after receiving the trigger signal.

Abstract: In an embodiment a control device includes a first input configured to receive a measurement signal representative of an output voltage of a switching circuit of a voltage regulator, a state determination block coupled to the first input and configured to generate a signal of actual operating condition of the voltage regulator and a driving signals generation module configured to generate at least one switching command signal for the switching circuit from an error signal representative of a difference between the output voltage and a nominal voltage, wherein the driving signals generation module includes an error-compensation circuit having a transfer function and configured to generate a control signal from the error signal and the actual operating condition signal, the control signal being a function of the actual operating condition.

Abstract: Electronic device, comprising: a semiconductor body having a surface, an electrical conductivity P and a first doping value; at least one gate region on the surface; one or more source regions, having a second electrical conductivity N, extending in the semiconductor body at the surface and at a first side of the gate region; and at least one body contact region, of P+ type, extending in the semiconductor body at the surface and at the first side of the gate region 22. The first gate region has the shape of a stripe with main extension along a first direction. The first body contact region has a tapered shape along said first direction. The one or more source regions are adjacent to, and at least partially surround, the first body contact region.

Abstract: A semiconductor electronic device has a substrate region of semiconductor material; a first electronic component based on heterostructure, which has an epitaxial multilayer that extends on the substrate region and includes a heterostructure; and a separation region that extends on the substrate region. The separation region includes a polycrystalline region of semiconductor material of polycrystalline type which is arranged, along a first direction, alongside the epitaxial multilayer. The electronic device also has an epitaxial region of a single semiconductor material of monocrystalline type which extends on the substrate region. The polycrystalline region extends, along the first direction, between the epitaxial multilayer and the epitaxial region.

Abstract: For manufacturing a semiconductor electronic device a wafer is provided which has a substrate layer of semiconductor material having a first portion and a second portion distinct from the first portion. An epitaxial region of a single semiconductor material is grown on the first portion of the substrate layer. An epitaxial multilayer having a heterostructure is grown on the second portion of the substrate layer. A first electronic component based on the single semiconductor material is formed from the epitaxial region and a second electronic component based on heterostructure is formed from the heterostructure. Forming a first electronic component comprises forming a plurality of doped regions in the epitaxial region, after the step of growing an epitaxial multilayer.

Abstract: A pixel includes a photosensitive circuit, a sense node, a first transistor and a first capacitor. A first electrode of the first capacitor is connected to a control terminal of the first transistor. A second electrode of the first capacitor is to a node of application of a first control signal.

Abstract: A method for manufacturing an ohmic contact for a HEMT device, comprising the steps of: forming a photoresist layer, on a semiconductor body comprising a heterostructure; forming, in the photoresist layer, an opening, through which a surface region of the semiconductor body is exposed at said heterostructure; etching the surface region of the semiconductor body using the photoresist layer as etching mask to form a trench in the heterostructure; depositing one or more metal layers in said trench and on the photoresist layer; and carrying out a process of lift-off of the photoresist layer.

Abstract: To manufacture a semiconductor electronic device a wafer is provided that has a substrate layer of semiconductor material having a first portion and a second portion distinct from the first portion. An epitaxial region of a single semiconductor material is grown on the first portion of the substrate layer. An epitaxial multilayer having a heterostructure is grown on the second portion of the substrate layer. A first electronic component based upon the single semiconductor material is formed starting from the epitaxial region and a second electronic component based upon a heterostructure is formed starting from the heterostructure. To grow an epitaxial multilayer, a growth mask is formed on the substrate layer; an opening is made in the growth mask, thereby exposing the second portion of the substrate layer; and the epitaxial multilayer is grown on the second portion of the substrate layer.

Abstract: A DC-DC converter includes a primary-side control-circuit having an oscillator driving a transformer in response to assertion of a PWM-signal to transmit power from the primary to the secondary and ceasing in response to deassertion of the PWM-signal, and a receiver demodulator circuit receiving/demodulating a feedback signal sent from the secondary to the primary by comparing an instantaneous value of an envelope indicative of voltages at the primary-coil to an average-value of the envelope to produce a reset-signal. A PWM circuit asserts the PWM-signal in response to a set-signal and deasserts the PWM-signal in response to assertion of the reset-signal. A secondary-side control-circuit rectifies the received power, asserts an intermediate feedback-signal if feedback indicative of the output voltage is greater than a reference-voltage, and connects a capacitance between the secondary and ground in response to assertion of the intermediate feedback-signal to modulate and send the feedback to the primary.

Abstract: Content is generated for a programmable computing device based on user-selected configuration information. The user-selected configuration information includes a user-selected versatile component. User-selectable versatile component configuration options for the user-selected versatile component are presented and versatile component configuration option selections for the user-selected versatile component are received. Settings for an instance of the user-selected versatile component are generated based on the received component configuration option selections. A configuration store is generated or updated based on the settings for the user-selected versatile component. Content for the programmable computing device is generated based on the configuration store.

Abstract: An HEMT device, comprising: a semiconductor body including a heterojunction structure; a dielectric layer on the semiconductor body; a gate electrode; a drain electrode, facing a first side of the gate electrode; and a source electrode, facing a second side opposite to the first side of the gate electrode; an auxiliary channel layer, which extends over the heterojunction structure between the gate electrode and the drain electrode, in electrical contact with the drain electrode and at a distance from the gate electrode, and forming an additional conductive path for charge carriers that flow between the source electrode and the drain electrode.