Abstract: A time based boost DC-DC converter generates an output voltage using an inductor. A voltage error between the output voltage and a reference voltage is determined and processed in a) an integral control branch which converts the voltage error into an integral control current signal used to control a current controlled oscillator, and b) a proportional branch which converts the voltage error into a proportional control current signal used to control signal a delay line. Current flowing in the inductor is sensed, attenuated and used to apply adjustment to the integral and proportional control current signals. The output from the current controlled oscillator is passed through the delay line and phase detected in order to generate pulse width modulation (PWM) control signaling driving switch operation in the converter.

Abstract: A leadframe has a die pad area and an outer layer of a first metal having a first oxidation potential. The leadframe is placed in contact with a solution containing a second metal having a second oxidation potential, the second oxidation potential being more negative than the first oxidation potential. Radiation energy is then applied to the die pad area of the leadframe contacted with the solution to cause a local increase in temperature of the leadframe. As a result of the temperature increase, a layer of said second metal is selectively provided at the die pad area of the leadframe by a galvanic displacement reaction. An oxidation of the outer layer of the leadframe is then performed to provide an enhancing layer which counters device package delamination.

Abstract: A digital signal processor includes K first electronic circuits. The first inputs receive K groups of G successive coefficients of a polynomial. The polynomial are of degree N with N+1 coefficients, where K is a sub-multiple of N+1 greater than or equal to two and G is equal to (N+1)/K. The first electronic circuits are configured to simultaneously implement K respective Horner methods and deliver K output results. A second electronic circuit includes a first input configured to successively receive the output results of the first electronic circuits starting with the output result of the first electronic circuit having processed the highest rank coefficient of the coefficients. A second input is configured to receive a variable X and the second electronic circuit is configured to implement a Horner method and deliver a value of the polynomial for the variable X on the output of the second electronic circuit.

Abstract: In an embodiment a non-volatile memory device includes a memory plane including at least one memory area including an array of memory cells having two rows and N columns, wherein each memory cell comprises a state transistor having a control gate and a floating gate selectable by a vertical selection transistor buried in a substrate and including a buried selection gate, and wherein each column of memory cells includes a pair of twin memory cells, two selection transistors of the pair of twin memory cells having a common selection gate and a processing device configured to store in the memory area information including a succession of N bits so that, with exception of the last bit of the succession, a current bit of the succession is stored in two memory cells located on the same row and on two adjacent columns and a current bit and the following bit are respectively stored in two twin cells.

Abstract: A method of making a light sensor module includes connecting a light sensing circuit to an interconnect on a substrate, and forming a cap. The cap is formed by producing a cap substrate from material opaque to light to have an opening formed therein, placing the cap substrate top-face down, dispensing a light transmissible material into the opening, compressing the light transmissible material using a hot tool to thereby cause the light transmissible material to fully flow into the opening to form at a light transmissible aperture, and placing the cap substrate into a curing environment. A bonding material is dispensed onto the substrate. The cap is picked up and placed onto the substrate positioned such that the light transmissible aperture is aligned with the light sensing circuit, with the bonding material bonding the cap to the substrate to thereby form the light sensor module.

Abstract: An embodiment device for synchronizing the emission and the reception of a light signal for a time-of-flight sensor comprises a power-control circuit configured to generate and transmit a power signal based on a control signal for controlling the sensor, the power signal being configured to supply power to an array of pixels of the sensor, a production module for producing a synchronization signal, which module is configured to produce the synchronization signal based on the control signal, and a switch configured to supply power to a light source of a device for emitting the light signal, the production module being further configured to transmit the synchronization signal to the switch such that the time taken to produce and transmit the synchronization signal and the time taken to generate and transmit the power signal are identical.

Abstract: An optoelectronic chip includes optical inputs having different passbands, a photonic circuit to be tested, and an optical coupling device configured to couple said inputs to the photonic circuit to be tested.

Abstract: A bipolar transistor includes a collector. The collector is formed by: a first portion of the collector which extends under an insulating trench, and a second portion of the collector which crosses through the insulating trench. The first and second portions of the collector are in physical contact.

Abstract: In an embodiment an electrically erasable programmable readable memory includes a plurality of memory cells organised in a memory plane arranged in a matrix fashion in rows and in columns, wherein each memory cell includes a state transistor having a source region, a drain region, an injection window situated on the side of the drain, a control gate and a floating gate and an isolation transistor having a source region, a drain region and a gate; and an isolation barrier including a buried layer and at least one wall extending from the buried layer to a surface of a substrate, wherein the at least one wall is perpendicular to the buried layer, and wherein the isolating barrier forms an interior substrate surrounding at least one of the memory cells and isolating it from the remainder of the substrate.

Abstract: An integrated circuit memory includes a state transistor having a floating gate which stores a respective data value. A device for protecting the data stored in the memory includes a capacitive structure having a first electrically-conducting body coupled to the floating gate of the state transistor, a dielectric body, and a second electrically-conducting body coupled to a ground terminal. The dielectric body is configured, if an aqueous solution is brought into contact with the dielectric body, to electrically couple the floating gate and the ground terminal so as to modify the charge on the floating gate and to lose the corresponding data. Otherwise, the dielectric body is configured to electrically isolate the floating gate and the ground terminal.

Abstract: An integrated circuit includes a substrate, an interconnection part, and an isolating region located between the substrate and the interconnection part. A decoy structure is located within the isolating region and includes a silicided sector which is electrically isolated from the substrate.

Abstract: A power MOSFET driver circuit includes a feedback circuit configured to supply a feedback signal that signals when a gate voltage of the power MOSFET crosses a plateau value and the power MOSFET switches conduction state. The feedback circuit includes a comparator with a replica MOSFET of the power MOSFET, with scaled down dimensions, whose gate is coupled to the gate electrode of the power MOSFET. A bistable circuit has an input coupled to an output of the replica MOSFET and is configured to change a logic state of the feedback signal following the transition of the switching signal when the gate voltage of the power MOSFET crosses the plateau value and the power MOSFET switches conduction state.

Abstract: A device includes an optical integrated circuit device mounted over an upper surface of a support substrate. The optical integrated circuit device includes an optical sensor array supported by a semiconductor substrate made of a first semiconductor material. A discrete semiconductor block, made of a second semiconductor material, is mounted over an upper surface of the optical integrated circuit device adjacent the optical sensor array. The first and second semiconductor materials have substantially matched coefficients of thermal expansion. A parallelpipedal-shaped optical filter is mounted over an upper surface of the discrete semiconductor block and extends over the optical sensor array. One or more edges/corners of the parallelpipedal-shaped optical filter cantilever over the optical sensor array without any provided support.

Abstract: A safety circuit for a gate driver device receives PWM driving signals, a system supply voltage, as well as first and second safety signals. The circuit includes a first logic circuit configured to propagate the PWM driving signals to produce gate driving signals if the first safety signal is de-asserted, and disable propagation of the PWM driving signals and de-assert the gate driving signals if the first safety signal is asserted. The circuit includes a second logic circuit configured to couple a power supply output node to the system supply voltage to produce a driver supply voltage if the second safety signal is de-asserted, and decouple the power supply output node from the system supply voltage if the second safety signal is asserted.

Abstract: A semiconductor product includes a layer of semiconductor die package molding material embedding a semiconductor die having a front surface and an array of electrically-conductive bodies such as spheres or balls around the semiconductor die. The electrically-conductive bodies have front end portions around the front surface of the semiconductor die and back end portions protruding from the layer of semiconductor die package molding material. Electrically-conductive formations are provided between the front surface of the semiconductor die and front end portions of the electrically-conductive bodies left uncovered by the package molding material. Light-permeable sealing material can be provided at electrically-conductive formations to facilitate inspecting the electrically-conductive formations via visual inspection through the light-permeable sealing material.

Abstract: The present disclosure relates to a method wherein a state of an integrated circuit between a first state (e.g., CLOSED), allowing a reading access to the first area of fuse-type non-volatile memory by a processor, and a second state (e.g., OPEN), forbidding the reading access to the memory to the processor, is conditioned to a verification, by a finite state machine, of values of a first fuse word of the memory, representative of a number of transitions to the first state and of a second fuse word of the memory, representative of a number of transitions to the second state.

Abstract: A device includes an analog to digital converter configured to convert voltages into a digital signal by sampling the voltages at a fixed sampling time; a first multiplier configured to multiply the digital signal with in-phase coefficients, the in-phase coefficients generated to produce a demodulated in-phase signal at a demodulation signal frequency; a first adder configured accumulate the demodulated in-phase signal to output in-phase magnitude values; a second multiplier configured to multiply the digital signal with quadrature coefficients, the quadrature coefficients generated to produce a demodulated quadrature signal at the demodulation signal frequency; and a second adder configured to accumulate the demodulated quadrature signal to output quadrature magnitude values.

Abstract: The present disclosure relates to a voltage source device comprising: a voltage converter for generating a supply voltage at an output node of the voltage converter based on a feedback signal provided on a feedback line; at least one switch coupled between the output node of the voltage converter and an output terminal of the voltage source device; and at least one further switch configured to selectively couple the feedback line to: the output node of the voltage converter during a first regulation mode; and to the output terminal of the voltage source device during a second regulation mode.

Abstract: A MEMS micromirror device is formed in a package including a containment body and a lid transparent to a light radiation. The package forms a cavity housing a tiltable platform having a reflecting surface. A metastructure is formed on the lid and/or on the reflecting surface and includes a plurality of diffractive optical elements.

Abstract: A phase-change memory (PCM) includes a semiconductor body housing a selection transistor; a electrical-insulation body disposed over the semiconductor body; a conductive region, extending through the electrical-insulation body, electrically coupled to the selection transistor; and a plurality of heater elements in the electrical-insulation body. Each of the plurality of heater elements include a first end in electrical contact with a respective portion of the conductive region and a second end that extends away from the conductive region. The PCM further includes a plurality of phase-change elements extending in the electrical-insulation body and including data storage regions, where each of the data storage regions being electrically and thermally coupled to one respective heater element at the second end of the respective heater element.