Abstract: A buck switching converter is calibrated using a method which alternates between first and second calibration phases. During each first calibration phase: a time period of low-side switch on state is kept constant and, for each current pulse in an inductor, a sign of a value of the current at the end of the time period of on state of the low-side switch is determined. Modification of a time period of high-side switch on state is made based on the determined sign. During each second calibration phase: a time period of high-side switch on state is kept constant and, for each current pulse in the inductor, a value of the current at the end of the time period of on state of the high-side switch is compared with a target value. Modification of the time period of low-side switch on state is made based on the comparison.

Abstract: The present disclosure relates to a pulse width modulation circuit of a switched-mode power supply formed in and on a monolithic semiconductor substrate with a face coated with a gallium nitride layer, said circuit being adapted to control a power transistor of said switched-mode power supply.

Abstract: An HEMT device is formed on a semiconductor body having a semiconductive heterostructure. A control region of a semiconductor material, is arranged on the semiconductor body and has a top surface and lateral sides. A control terminal, of conductive material, extends on and in contact with the top surface of the control region. A passivation layer of non-conductive material, extends on the semiconductor body, partially on the top surface of the control region and on the lateral sides of the control region, laterally and at a distance from the control terminal.

Abstract: Disclosed herein are thermal sensor devices including TMOS devices with a mass suspended over a cavity by springs extending between a frame and the mass. The thermal sensor devices include stoppers that limit upward and/or downward movement of the springs and therefore the mass. These stoppers are formed from sidewalls supporting a top cap over the frame, springs, and mass. The stoppers are constructed by using various overlapping metal layers during fabrication. Details of forming the stoppers using these overlapping metal layers are contained here.

Abstract: An integrated circuit includes an overvoltage protection circuit. The overvoltage protection circuit detects overvoltage events at a pad of the integrated circuit. The overvoltage protection circuit generates a max voltage signal that is the greater of the voltage at the pad and a supply voltage of the integrated circuit. The overvoltage protection circuit disables a PMOS transistor coupled to the pad by supplying the max voltage signal to the gate of the PMOS transistor when an overvoltage event is present at the pad.

Abstract: A MEMS device is formed by a body of semiconductor material which defines a support structure. A pass-through cavity in the body is surrounded by the support structure. A movable structure is suspended in the pass-through cavity. An elastic structure extends in the pass-through cavity between the support structure and the movable structure. The elastic structure has a first and second portions and is subject, in use, to mechanical stress. The MEMS device is further formed by a metal region, which extends on the first portion of the elastic structure, and by a buried cavity in the elastic structure. The buried cavity extends between the first and the second portions of the elastic structure.

Abstract: A system to monitor a MOSFET, the system including a switching arrangement configured to switchably isolate a gate terminal of the MOSFET and a source terminal of the MOSFET from a gate-control voltage source and a test circuit configured to detect a change in a gate-to-source voltage of the MOSFET over a test period, the test period occurring while the gate terminal and the source terminal are isolated.

Abstract: A photodiode is formed in a semiconductor substrate of a first conductivity type. The photodiode includes a first region having a substantially hemispherical shape and a substantially hemispherical core of a second conductivity type, different from the first conductivity type, within the first region. An epitaxial layer covers the semiconductor substrate and buries the first region and core.

Abstract: A voltage-controlled oscillator in a phase-locked loop circuit is calibrated via a dichotomous search in a set of candidate frequency bands via a sequence of subsequent halving steps that produce reduced subsets of the set of candidate frequency bands. The reduced subsets have respective upper bound values and lower bound values, as well as central values. The central value of the subset resulting from the halving step of index i in the sequence is a function of the average of the upper bound value and the lower bound value of the subset resulting from the halving step of index i?1 in the sequence.

Abstract: SRAM cells are connected in columns by bit lines and connected in rows by first and second word lines coupled to first and second data storage sides of the SRAM cells. First the first word lines are actuated in parallel and then next the second word lines are actuated in parallel in first and second phases, respectively, of an in-memory compute operation. Bit line voltages in the first and second phases are processed to generate an in-memory compute operation decision. A low supply node reference voltage for the SRAM cells is selectively modulated between a ground voltage and a negative voltage. The first data storage side receives the negative voltage and the second data storage side receives the ground voltage during the second phase. Conversely, the second data storage side receives the negative voltage and the first data storage side receives the ground voltage during the first phase.

Abstract: A continuous time, sigma-delta analog-to-digital converter circuit includes a sigma-delta modulator circuit configured to receive an analog input signal. A single bit quantizer of the modulator generates a digital output signal at a sampling frequency. A data storage circuit stores bits of the digital output signal and digital-to-analog converter (DAC) elements are actuated in response to the stored bits to generate an analog feedback signal for comparison to the analog input signal. A filter circuit includes polyphase signal processing paths and a summation circuit configured to sum outputs from the polyphase signal processing paths to generate a converted output signal. A fan out circuit selectively applies the stored bits from the data storage circuit to inputs of the polyphase signal processing paths of the filter circuit.

Abstract: The present disclosure relates to a method of communication via serial bus, comprising: the conveyance by the serial bus of a frame comprising at least two consecutive cycles of a dominant state followed by a recessive state, the recessive states and dominant states having durations comprised between 2 and 5 times the duration of a data bit conveyed by the serial bus, and preferably above 1.8 ?s; and the detection by one or more circuits coupled to the serial bus of at least a part of the frame for triggering the passage from a sleep state to a wake state of the one or more circuits.

Abstract: A system includes a control unit configured to be electrically connected to an input of a memory via a communication interface. The control unit includes a first power supply sector configured to be powered when the control unit is in an operating mode and a second power supply sector configured to be powered when the control unit is in the operating mode and in a low consumption mode. In the first power supply sector, the control unit includes a first configuration circuit operating to configure a polarization value of the input of the memory via the communication interface for the operating mode. In the second power supply sector, the control unit includes a second configuration circuit operating to configure a polarization value of the input of the memory via the communication interface for the low consumption mode.

Abstract: A method for fabricating a semiconductor chip includes forming a plurality of conducting pads at a front face of a substrate, thinning a rear face of the substrate, etching openings under each conducting pad from the rear face, depositing a layer of a dielectric on walls and a bottom of the openings, forming a conducting material in the openings, and forming a conducting strip on the rear face. The conducting strip is electrically connected to the conducting material of each of the openings. The etching is stopped when the respective conducting pad is reached.

Abstract: A first multiplier multiplies a first input with a first coefficient and a first adder sums an output of the first multiplier and a second input to generate a first output. A second multiplier multiplies a third input with a second coefficient, a third multiplier multiplies a fourth input with a third coefficient, and a second adder sums outputs of the second and third multipliers to generate a second output. The second and third inputs are derived from the first output and the first and fourth inputs are derived from the second output. The first and second outputs generate digital values for first and second digital sinusoids, respectively.

Abstract: A touch status monitor method includes detecting a touch on a touch screen when operating in a low-power detect scan mode. The method further includes, in response to detecting the touch, switching from the low-power detect scan mode to a low-power active scan mode and labeling the current event as a touch down event. The method further includes, in response to labeling the current event as the touch down event, applying a lock to prevent updating a baseline when entering the low-power detect scan mode. And the method further includes, in response to detecting that the touch has left the touch screen, releasing the lock, labeling the current event as a touch up event, switching from the low-power active scan mode to the low-power detect scan mode, and updating the baseline.

Abstract: A circuit includes a first and a second memory, a processor and a timer. The processor generates a sequence of bits encoding a CAN frame and processes the sequence of bits to detect a sequence of PWM periods. The processor stores values of a first parameter of the PWM periods into the first memory, and values of a second parameter of the PWM periods into the second memory. The timer comprises a first register which reads from the first memory a value of the first parameter of a current PWM period. The timer comprises a counter which increases a count number and resets the count number as a function of the value of the first register.

Abstract: Method of manufacturing an electronic device, comprising the steps of: arranging a semiconductor body of N-type, having a lattice structure with spatial symmetry, comprising an active area an edge region surrounding the active area; forming, in the edge region, an intentionally damaged region wherein the lattice structure has no spatial symmetry; forming an edge termination region of P-type at the damaged region, by random implant; forming a current spreading layer, CSL, in the edge region at and lateral to the damaged region, by channeled implant. The CSL has, at the damaged region, a minimum thickness and, laterally to the damaged region, a maximum thickness. The minimum thickness is lower than the thickness of the edge termination region.

Abstract: A process for manufacturing a power electronic device, envisages: forming a semiconductor body of silicon carbide, having a first electrical conductivity and a first doping value, and defining a front surface; forming a Current Spreading Layer, CSL, in a surface portion of said semiconductor body facing the front surface, having the first electrical conductivity and a second doping value, greater than the first doping value; forming elementary cells of the power electronic device in an active area of the semiconductor body at the front surface. The step of forming the current spreading layer envisages performing a channeled ion implantation, in a channeling condition, for implanting doping ions having the first electrical conductivity within the semiconductor body.

Abstract: A system includes a write-data register and a read-data register, each clocked by a clock signal, and a first-in-first-out (FIFO) buffer coupled between the write-data register and the read-data register, the FIFO buffer including latches configured to store data. The system further includes glue logic with first, second, and third logic circuits configured to generate an internal write enable signal, an internal read valid signal, and an internal read enable signal based on an operational mode of the system. The system is configured to be selectively switched between a normal operational mode, where the latches are accessed for reading and writing by a read enable signal and write enable signal based on a read address signal and a write address signal, and a transition testing mode, where the latches are tested using the internal write enable signal, the internal read enable signal, and the internal read valid signal.