Abstract: Blood pressure signals are reconstructed from PhotoPlethysmoGraphy (PPG) signals by: receiving PPG signals including systolic, diastolic and dicrotic phases; and determining first and second derivatives of the PPG signals and: a first set of values indicative of lengths of the signal paths of the PPG signal, the first derivative and the second derivative thereof in the systolic, diastolic and dicrotic phases; a second set of values indicative of relative durations of the PPG signal and the first and second derivatives thereof in the systolic, diastolic and dicrotic phases; and a third set of values indicative of the time separation of peaks and/or valleys in subsequent waveforms of the PPG signal. Reconstruction also includes applying artificial neural network processing to the first, second and third set of values. The artificial neural network processing includes artificial neural network training as a function of blood pressure signals to produce reconstructed blood pressure signals.

Abstract: A first node of converter circuit receives an input, provides an output at a second node, and has a third node coupled by an inductance to ground. A first switch has a current path between the first and third nodes and a second switch has a current path between the third and second nodes. The converter circuit operates in a first state (with the first switch conductive and the second switch non-conductive) and a second state (with the first switch non-conductive and the second switch conductive). Current flowing through the first switch is sensed during the first state to produce a sensing signal indicative of inductance current. The sensing signal is averaged to produce an averaged sensing signal indicative of an average value of the current. The averaged sensing signal is then weighted by a time during which the second switch is conductive to produce a weighted signal.

Abstract: A system-on-a-chip (SOC) within a package includes a reference generator, a matching circuit, a programmable current generator, a PWM controller, an overvoltage/undervoltage detector receiving a high voltage from a third output pad, a multiplexer passing an input signal to a second output pad, and a SPAD receiving the high voltage. Switching circuitry includes a first switch between the reference generator and an input of the programmable current generator, a second switch between the input of the current generator and the output of the matching circuit, a third switch between the reference generator and an input of the matching circuit, a fourth switch between an output of the current generator and a tap of a ladder within the overvoltage/undervoltage detector, a fifth switch between an output of the current generator and the first output pad, and a sixth switch between the output of the PWM controller and the first output pad.

Abstract: A system for diagnosing the operating state of a MEMS sensor includes a stimulation circuit, external to the MEMS sensor, configured to generate a stimulation signal designed to be detected by the MEMS sensor. The system has control circuitry, operatively coupled to the stimulation circuit and to the MEMS sensor, so as to control the stimulation circuit to generate the stimulation signal and receive a diagnostic signal generated by the MEMS sensor in response to the stimulation signal. The control circuitry determines an operating state of the MEMS sensor based on the diagnostic signal and an expected response to the stimulation signal by the MEMS sensor.

Abstract: A processing system includes a processing core including a microprocessor, a memory controller configured to read software instructions for execution by the processing core, a plurality of safety monitoring circuits configured to generate a plurality of error signals by monitoring operation of the processing core and the memory controller, a fault collection and error management circuit implemented as a hardware circuit, and a connectivity test circuit. The fault collection and error management circuit is configured to receive the plurality of error signals from the plurality of safety monitoring circuits and generate one or more reaction signals as a function of the plurality of error signals. The connectivity test circuit is configured to, during a diagnostic phase executed by the processing system after executing a reset phase and before executing a software runtime phase, test connectivity between the plurality of safety monitoring circuits and the fault collection and error management circuit.

Abstract: A method can be used for verifying an execution of a compiled software program stored in a program memory of a processor and executed by the processor. A write operation includes assigning a destination address in a register of the processor and writing a datum at a location pointed to by the destination address contained in the register. A verification operation includes reassigning the same destination address in the same register, reading the datum contained at the location pointed to by the destination address contained in the register after the reassignment, and comparing the read datum and the written datum.

Abstract: The present description concerns a ROM including at least one first rewritable memory cell. In an embodiment, a method of manufacturing a read-only memory (ROM) comprising a plurality of memory cells is proposed. Each of the plurality of memory cells includes a rewritable first transistor and a rewritable second transistor. An insulated gate of the rewritable first transistor is connected to an insulated gate of the rewritable second transistor. The method includes successively depositing, on a semiconductor structure, a first insulating layer and a first gate layer, wherein the first insulating layer is arranged between the semiconductor structure and the first gate layer, wherein the rewritable second transistor further includes a well-formed between an associated first insulating layer and the semiconductor structure, and wherein the rewritable first insulating layer is in direct contact with the semiconductor structure; and successively depositing a second insulating layer and a second gate layer.

Abstract: A time based boost DC-DC converter generates an output voltage using an inductor. A voltage error between the output voltage and a reference voltage is determined and processed in a) an integral control branch which converts the voltage error into an integral control current signal used to control a current controlled oscillator, and b) a proportional branch which converts the voltage error into a proportional control current signal used to control signal a delay line. Current flowing in the inductor is sensed, attenuated and used to apply adjustment to the integral and proportional control current signals. The output from the current controlled oscillator is passed through the delay line and phase detected in order to generate pulse width modulation (PWM) control signaling driving switch operation in the converter.

Abstract: A method is presented for verifying a writing of a key into a non-volatile memory. A first cyclic redundancy code of the key is stored into a register of an interface of the memory. A second cyclic redundancy code is computed on a message formed by the copied key having the first cyclic redundancy code linked thereto. The writing of the key into the non-volatile memory is considered as valid when the second cyclic redundancy code is equivalent to the zero value.

Abstract: A multi-zone illumination system includes a light source formed by first emitters configured to transmit a first light signal having a first polarization state and second emitters configured to transmit a second light signal having a second polarization state transverse to the first polarization state. An optic receives the first light signal and generates a first structured illumination of a first far field zone. The optic further receives the second light signal and generates a second structured illumination of a second far field zone. The first and second far field zones are offset from each other.

Abstract: The present disclosure concerns a method of forming an electronic power component inside and on top of a semiconductor substrate, comprising the following successive steps: a) forming of a peripheral groove in the semiconductor substrate on the side of a first surface of the semiconductor substrate; b) deposition of an oxygen-doped polysilicon layer, on top of and in contact with the bottom and the lateral walls of the peripheral groove and with the first surface of the semiconductor substrate; c) local deposition of a glass layer, on the oxygen-doped polysilicon layer, the glass layer extending in the peripheral groove and further extending over a portion of the first surface of the semiconductor substrate; and d) etching of the oxygen-doped polysilicon layer so that it extends on the first surface of the semiconductor substrate beyond the glass layer.

Abstract: The present disclosure relates to a method of forming an HEMT transistor, comprising the following successive steps: a) providing a stack comprising a semiconductor channel layer, a semiconductor barrier layer on top of and in contact with the semiconductor channel layer, and a semiconductor gate layer arranged on top of and in contact with the semiconductor barrier layer, the semiconductor gate layer comprising P-type dopant elements; and b) compensating for the P-type doping with oxygen atoms, in an upper portion of the semiconductor gate layer, by an oxygen anneal, so as to define a PN junction at the interface between the upper portion and a central portion of the semiconductor gate layer.

Abstract: A processor of a processing device executes a boot code to carry out a boot sequence of the processing device. The execution includes at least one verification step for verifying a proper progress of the boot sequence. When the verification step identifies an error in the progress of the boot sequence, a status value (with an indication that an error occurred during that verification step) is stored in a register of the processing device. The processing device is then reset. The register is accessible in read mode via a debugging interface of the processing device.

Abstract: An integrated circuit includes a semiconductor substrate patterned to include a first semiconductor track and a second semiconductor track separated from each other by a trench isolation region. The integrated circuit includes a logic circuit including a transistor having a first drain subregion in the first semiconductor track, a second drain subregion in the second semiconductor track, a first source subregion in the first semiconductor track, and a second source subregion in the second semiconductor track. A diffusion bridge of semiconductor material extends between the first and second semiconductor tracks and connects the first source subregion to the second source subregion. The first drain subregion and the second drain subregion are electrically connected by a drain metalization.

Abstract: In a method of emulation of N boot programs in a memory, N being an integer greater than 2, the size of a no-access region of the memory containing the boot programs is increased in response to execution of each boot program.

Abstract: EEPROM emulation is provided in a phase-change memory of a circuit integrating a microprocessor. A granularity for writing into lines of the phase-change memory is defined according to a size of data packets to be written. A first error correction code calculated by a program executed by said microprocessor is associated with each data packet. Several data packets and their associated first error correction codes are then stored in a same line of the phase-change memory data packet.

Abstract: In providing electrical wire-like connections between at least one semiconductor die arranged on a semiconductor die mounting area of a substrate and an array of electrically-conductive leads in the substrate, pressure force is applied to the electrically-conductive leads in the substrate during bonding the wire-like connections to the electrically-conductive leads. Such a pressure force is applied to the electrically-conductive leads in the substrate via a pair of mutually co-operating force transmitting surfaces. These surfaces include a first convex surface engaging a second concave surface.

Abstract: A UART communication interface manages transmission/reception at a baud rate using a baud-rate detection circuit. An edge detector detects edges in a reception signal and resets a count value in a digital counter circuit indicating a time between two consecutive edges. In the absence of a detected edge, the digital counter circuit increases the count value. At a newly detected edge, a validation circuit verifies the count value by asserting a second control signal when the count value is smaller than a maximum, and otherwise de-asserting the second control signal. A register provides a threshold signal by storing the count value when the second control signal is asserted. The threshold signal stored by the register is updated when the time is in a permitted range corresponding to the duration of a single bit. The baud rate may be determined as a function of the threshold signal.

Abstract: In an embodiment a method for detecting a presence of at least one object in a field of view of a time of flight sensor includes successively generating, by the time of flight sensor, histograms, each histogram comprising several classes associating a number of photons detected at a given acquisition period, adding several successively generated histograms so as to obtain a summed histogram and analyzing the summed histogram to detect the presence of at least one object in the field of view of the time of flight sensor.

Abstract: A sensing pixel includes a single photon avalanche diode (SPAD) coupled between a first node and a second node, with a clamp diode being coupled between a turn-off voltage node and the second node. A turn-off circuit includes a sense circuit configured to generate a feedback voltage based upon a voltage at the turn-off voltage node, a transistor having a first conduction terminal coupled to the turn-off voltage node, a second conduction terminal coupled to ground, and a control terminal, and an amplifier having a first input coupled to a reference voltage, a second input coupled to receive the feedback voltage, and an output coupled to the control terminal of the transistor. A readout circuit is coupled to the SPAD by a decoupling capacitor.