Patents Assigned to STMicroelectronics (Research & Development) Ltd.
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Patent number: 11966537Abstract: A method for operating an electronic device, including: determining that a touchscreen is in a low frequency display (LFD) mode, determining whether a self-sensing scan was performed in a previous frame of a plurality of frames; after determining, a self-sensing scan was performed in the previous frame, determining a current duration of time corresponding to a current frame based on a previous duration of time corresponding to the previous frame, the previous frame being a frame immediately preceding the current frame; determining, whether the current duration of time is greater than the previous duration of time; and after determining that the current duration is greater than the previous duration, performing a self-sensing scan after the current duration of time, the current duration of time being measured from a beginning of the current frame, the current duration of time having a duration less than a duration of the current frame.Type: GrantFiled: February 20, 2023Date of Patent: April 23, 2024Assignee: STMicroelectronics Asia Pacific Pte Ltd.Inventors: Sang soo Lee, Chan Hyuck Yun
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Patent number: 11967544Abstract: In providing electrical wire-like connections between at least one semiconductor die arranged on a semiconductor die mounting area of a substrate and an array of electrically-conductive leads in the substrate, pressure force is applied to the electrically-conductive leads in the substrate during bonding the wire-like connections to the electrically-conductive leads. Such a pressure force is applied to the electrically-conductive leads in the substrate via a pair of mutually co-operating force transmitting surfaces. These surfaces include a first convex surface engaging a second concave surface.Type: GrantFiled: May 19, 2021Date of Patent: April 23, 2024Assignee: STMicroelectronics S.r.l.Inventors: Mauro Mazzola, Matteo De Santa
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Publication number: 20240128871Abstract: A boost DC-DC converter includes a switching network, coupled to an inductor, controlled by a PWM driving signal. A control loop receives a voltage output and provides the PWM driving signal. The control loop generates an error signal as a function of a difference between voltage output voltage and a reference, with the PWM driving signal generated based on the error signal. A low pass filter circuit within the control loop receives the PWM driving signal and provides at least one filtered signal. An adder node of the control loop receives the at least one filtered signal from the low pass filter circuit for addition to the at least one filtered signal. The PWM driving signal is generated as a function of a sum of the filtered signal and the error signal.Type: ApplicationFiled: October 3, 2023Publication date: April 18, 2024Applicant: STMicroelectronics S.r.l.Inventors: Alessandro BERTOLINI, Alessandro GASPARINI, Paolo MELILLO, Salvatore LEVANTINO, Massimo GHIONI
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Publication number: 20240124300Abstract: A semiconductor package that contains an application-specific integrated circuit (ASIC) die and a micro-electromechanical system (MEMS) die. The MEMS die and the ASIC die are coupled to a substrate that includes an opening that extends through the substrate and is in fluid communication with an air cavity positioned between and separating the MEMS die from the substrate. The opening exposes the air cavity to an external environment and, following this, the air cavity exposes a MEMS element of the MEMS die to the external environment. The air cavity separating the MEMS die from the substrate is formed with a method of manufacturing that utilizes a thermally decomposable die attach material.Type: ApplicationFiled: December 27, 2023Publication date: April 18, 2024Applicant: STMicroelectronics, Inc.Inventor: Jefferson Sismundo TALLEDO
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Publication number: 20240128203Abstract: A method of manufacturing a chip-sized package includes providing a wafer having a die area formed therein adjacent a front face thereof, with the die area having pads formed thereon. Vias in the wafer are formed to extend between a back face of the wafer and a back side of some of the pads of the die area. Solder pads connected to the vias are formed, and a thermal pad is formed on the back side of the wafer opposite to the die area. Cavities are formed in the back face of the wafer to define pillars extending outwardly from a planar portion of the die area, some of the pillars having the solder pads at a distal end thereof, at least one of the pillars having the thermal pad at a distal end thereof. The wafer is singulated to form a chip-sized package including an integrated circuit die.Type: ApplicationFiled: September 18, 2023Publication date: April 18, 2024Applicant: STMicroelectronics PTE LTDInventor: Jing-En LUAN
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Publication number: 20240128289Abstract: The present disclosure concerns an image sensor including a plurality of pixels, each including: a doped photosensitive region of a first conductivity type extending vertically in a semiconductor substrate; a charge collection region more heavily doped with the first conductivity type than the photosensitive region, extending vertically in the substrate from an upper surface of the substrate and being arranged above the photosensitive region; and a vertical stack including a vertical transfer gate and a vertical electric insulation wall, the stack crossing the substrate and being in contact with the charge collection region, the gate being arranged on the upper surface side of the substrate and penetrating into the substrate deeper than the charge collection region.Type: ApplicationFiled: December 20, 2023Publication date: April 18, 2024Applicant: STMicroelectronics (Crolles 2) SASInventors: Francois ROY, Andrej SULER
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Publication number: 20240125930Abstract: A method is for detecting one or more objects in a detection zone using a time-of-flight sensor. The method includes emitting optical radiation via the emission circuitry of the sensor and subsequently capturing the reflected optical radiation using the reception circuitry. This captured radiation is quantified in terms of photons, and measurement circuitry determines both the amount of these photons and the distance from the sensor to the object(s). An analysis of the photon count, combined with the calculated distance, is used to determine the presence or absence of objects within the detection zone.Type: ApplicationFiled: October 9, 2023Publication date: April 18, 2024Applicants: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics Design and Application S.R.O., STMicroelectronics (Alps) SASInventors: Robin VASSAL, Jiri ANDRLE, Peter CABAJ, Cyrille TROUILLEAU
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Publication number: 20240125992Abstract: The present description concerns an optical filter intended to be arranged in front of an image sensor comprising a plurality of pixels, the filter comprising, for each pixel, a resonant cavity comprising a first transparent layer, interposed between second and third mirror layers, and a diffraction grating formed in the first layer, wherein at least one of the cavities has a different thickness than another cavity.Type: ApplicationFiled: March 28, 2023Publication date: April 18, 2024Applicants: STMicroelectronics (Crolles 2) SAS, COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Quentin ABADIE, Sandrine VILLENAVE
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Publication number: 20240128971Abstract: An integrated circuit includes a current mode transmitter having a first driver and a second driver. The first driver receives a single bit data stream. The second driver receives a delayed data stream corresponding to the single bit data stream delayed by a clock cycle. The current mode transmitter has a transition detector that generates a bulk modulation signal having a first value when the single bit data stream is the same as the delayed data stream and having a second value when the single bit data stream is different from the delayed data stream. The transition detector supplies the bulk modulation signal to the bulk terminals of driver switches of the first and second drivers.Type: ApplicationFiled: October 5, 2023Publication date: April 18, 2024Applicant: STMicroelectronics International N.V.Inventors: Sameer VASHISHTHA, Saiyid Mohammad Irshad RIZVI, Paras GARG
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Patent number: 11959995Abstract: A PLL has a tunable resonator including an inductance and variable capacitance coupled between first and second nodes, and capacitances coupleable between the nodes. A control node is coupled to the variable capacitance and receives a control signal for tuning the resonator. A biasing circuit biases the resonator to generate an output. A PFD circuit senses timing offset of the output with respect to a reference and asserts first or second digital signals dependent on the sign of the timing offset. A charge pump generates the control signal based on the first and second digital signals. A timer asserts a timing signal in response to a pulse sensed in a reset signal and de-asserts the timing signal after a time interval. A calibrator couples selected capacitances between the first and second nodes as a function of the second digital signal, in response to assertion of the timing signal.Type: GrantFiled: August 5, 2021Date of Patent: April 16, 2024Assignee: STMicroelectronics S.r.l.Inventors: Alessandro Finocchiaro, Alessandro Parisi, Andrea Cavarra, Giuseppe Papotto, Giuseppe Palmisano
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Patent number: 11962677Abstract: A method of processing a data stream includes taking a first number of samples of the data stream using a sampling clock over a first observation window and storing a stored data stream including the first number of samples in a data buffer. A length of the first observation window is determined by a reference clock. A measured number of cycles of the sampling clock are determined from the first number of samples. An error between an expected number of cycles of the sampling clock and the measured number of cycles of the sampling clock in the observation window is measured. The stored data stream corresponding to the first observation window is updated to contain a second number of samples by correcting the first number of samples with the error.Type: GrantFiled: April 13, 2022Date of Patent: April 16, 2024Assignee: STMicroelectronics S.r.l.Inventors: Francesco Pappalardo, Elena Salurso
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Patent number: 11962462Abstract: System on a chip, comprising several master pieces of equipment, several slave resources, an interconnection circuit capable of routing transactions between master pieces of equipment and slave resources, and a processing unit at least configured to allow a user of the system on a chip to implement within the system on a chip at least one configuration diagram of this system defined by a set of configuration pieces of information including at least one piece of identification information assigned to each master piece of equipment, The identification pieces of information are intended to be attached to all the transactions emitted by the corresponding master pieces of equipment, the set of configuration pieces of information not being used for addressing the slave resources receiving the transactions and being used to define an assignment of at least one piece of master equipment to at least some of the slave resources.Type: GrantFiled: May 22, 2023Date of Patent: April 16, 2024Assignees: STMicroelectronics (Alps) SAS, STMicroelectronics (Grand Ouest) SASInventors: Nicolas Anquet, Loic Pallardy
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Patent number: 11961868Abstract: A back side illuminated image sensor includes a pixel formed by three doped photosensitive regions that are superposed vertically in a semiconductor substrate. Each photosensitive region is laterally framed by a respective vertical annular gate. The vertical annular gates are biased by a control circuit during an integration phase so as to generate an electrostatic potential comprising potential wells in the central portion of the volume of each doped photosensitive region and a potential barrier at each interface between two neighboring doped photosensitive regions.Type: GrantFiled: May 17, 2023Date of Patent: April 16, 2024Assignee: STMicroelectronics (Crolles 2) SASInventor: Francois Roy
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Patent number: 11960033Abstract: Described herein is a time-of-flight ranging system and methods for its operation. The system includes an array of single photon avalanche diode (SPAD) pixels and control circuitry. The control circuitry simultaneously accumulates integrated SPAD event data from one cluster of SPAD pixels while integrating SPAD event data from another cluster during different target illuminations. The system also includes first and second VCSEL clusters, each responsible for a different target illumination. By processing and managing the data in this manner, the system can effectively reduce the time used to gather and analyze the event data, leading to faster and more accurate distance measurements.Type: GrantFiled: March 24, 2023Date of Patent: April 16, 2024Assignee: STMicroelectronics (Grenoble 2) SASInventor: Pascal Mellot
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Publication number: 20240120838Abstract: In a DC-DC converter, a duty-cycle control signal is generated in response to comparing the switching stage output voltage and a reference voltage signal. A first circuit compares the duty-cycle control signal and a ramp to produce a PWM signal. A second circuit compares the duty-cycle control signal and a skip threshold to produce a skip control signal which halts switching operation of the switching stage. A count is made of number of periods of the skip control signal during a monitoring time window and the number of periods of a clock signal during a period of the skip control signal is counted. When the counted number of skip control signal periods is within a first range and the counted number of clock signal periods is within a second range, a common detection signal is asserted to trigger varying a value of the skip threshold signal.Type: ApplicationFiled: October 3, 2023Publication date: April 11, 2024Applicant: STMicroelectronics S.r.l.Inventors: Alessandro BERTOLINI, Alberto CATTANI, Alessandro GASPARINI
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Publication number: 20240120638Abstract: An electronic device includes a first layer with an antenna and a second metal layer that extends over the entire first layer. The second metal layer includes at least one laterally-closed cavity that is located vertically above the antenna. The cavity is filled, at least in part, by a resin material. A first plate supporting a second metal plate extends over the cavity with the second metal plate positioned vertically above the antenna. The first metal plate may be supported by a ledge within the cavity. Alternatively, the second metal plate is embedded in the resin filling the cavity, with the second metal plate positioned vertically above the antenna.Type: ApplicationFiled: December 19, 2023Publication date: April 11, 2024Applicant: STMicroelectronics (Alps) SASInventor: Deborah COGONI
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Publication number: 20240120301Abstract: A back end of line (BEOL) structure for an integrated circuit chip includes a last metal structure providing a bonding pad. A passivation structure over the bonding pad includes a first opening extending exposing an upper surface of the bonding pad. A conformal nitride layer extends over the passivation structure and is placed in contact with the upper surface of the bonding pad. An insulator material layer covers the conformal nitride layer and includes a second opening that extends through both the insulator material layer and the conformal nitride layer. A foot portion of the conformal nitride layer on the upper surface of the bonding pad is self-aligned with the second opening.Type: ApplicationFiled: December 19, 2023Publication date: April 11, 2024Applicant: STMicroelectronics S.r.l.Inventors: Simone Dario MARIANI, Elisabetta PIZZI, Daria DORIA
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Publication number: 20240120267Abstract: A warped semiconductor die is attached onto a substrate such as a leadframe by dispensing a first mass of die attach material onto an area of the substrate followed by dispensing a second mass of die attach material so that the second mass of die attach material provides a raised formation of die attach material. For instance, the second mass may be deposited centrally of the first mass. The semiconductor die is placed onto the first and second mass of die attach material with its concave/convex shape matching the distribution of the die attach material thus effectively countering undesired entrapment of air.Type: ApplicationFiled: December 20, 2023Publication date: April 11, 2024Applicants: STMicroelectronics S.r.l., STMicroelectronics SDN BHDInventors: Andrea ALBERTINETTI, Marifi Corregidor CAGUD
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Patent number: 11954548Abstract: A connector that is configured to receive a smart card includes: a first contact configured to receive a power supply voltage and corresponding to a first (power supply) contact area of the smart card, a second contact configured to receive a reference voltage and corresponding to contact a second (reference voltage) contact area of the smart card, and a third contact corresponding to a three-state (input/output) contact area of the smart card. A first light-emitting diode having an anode coupled to the third contact and a cathode coupled to the second contact. A second light-emitting diode has a cathode coupled to the third contact and an anode coupled to the first contact. Turning on/off of the first and second light-emitting diode is controlled by the smart card through the signal at the three-state (input/output) contact area.Type: GrantFiled: November 5, 2021Date of Patent: April 9, 2024Assignees: STMicroelectronics (Grand Ouest) SAS, STMicroelectronics (Rousset) SASInventors: Frederic Gouabau, Olivier Rouy
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Patent number: 11950911Abstract: An embodiment method comprises collecting at least one electrophysiological signal of a human over a limited time duration, and computing a set of electrophysiological signal features. The computing comprises at least one of: providing at least one reference electrophysiological signal and applying dynamic time warping processing to the at least one collected and at least one reference electrophysiological signals, applying stacked-auto-encoder artificial neural network processing to the collected electrophysiological signal, or filtering the electrophysiological signal collected via joint low-pass and high-pass filtering. The method further comprises applying pattern recognition processing to the computed set of features, producing a virtual key signal indicative of an identity of the human, and applying the virtual key signal to a user circuit to switch it between a first state and a second state as a result of the virtual key signal matching an authorized key signal stored in the user circuit.Type: GrantFiled: September 1, 2020Date of Patent: April 9, 2024Assignee: STMicroelectronics S.r.l.Inventors: Francesco Rundo, Sabrina Conoci, Concetto Spampinato