Patents Assigned to STMicroelectronics (Rousset) SAS
  • DETECTION OF A TIME CONDITION RELATIVE TO A TWO-WIRE BUS
    Publication number: 20190102328
    Abstract: A value representative of a duration of the low state of a synchronization signal on a bus is measured and then compared with a threshold value. The threshold value is stored in a memory and the measured value represents, in a first comparison, a longest duration of the low states of the synchronization signal.
    Type: Application
    Filed: October 1, 2018
    Publication date: April 4, 2019
    Applicant: STMicroelectronics (Rousset) SAS
    Inventor: Francois TAILLIET
  • Adaptation of an antenna circuit for a near-field communication terminal
    Patent number: 10249946
    Abstract: A method for adapting an antenna circuit including at least one first capacitive element and an inductive element in series, and at least one second capacitive element having a first electrode connected between the first capacitive element and the inductive element, wherein data representative of the voltage of said first electrode are applied to the second electrode of the second capacitive element.
    Type: Grant
    Filed: June 10, 2013
    Date of Patent: April 2, 2019
    Assignees: STMicroelectronics (Rousset) SAS, Melexis Technologies SA
    Inventors: Thierry Meziache, Oleksandr Zhuk
  • Method and circuit for protecting and verifying address data
    Patent number: 10248580
    Abstract: A circuit is for protecting memory address data. The circuit may include an input data bus configured to receive write data to be written to a memory device, and an address bus configured to receive a corresponding write address. The circuit may also include an output data bus, and an address protection circuit coupled to the input data, address, and output data buses and configured to generate an address protection value based on the corresponding write address, and generate modified write data, on the output data bus. The modified write data includes the write data and the address protection value. The output data bus may have a width greater than a width of the input data bus.
    Type: Grant
    Filed: February 29, 2016
    Date of Patent: April 2, 2019
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Eric Bernasconi, Richard O'Connor
  • Method of wireless communication using thermoelectric generators
    Patent number: 10249679
    Abstract: Method of wireless communication between a first device and a second device, in which, the first device and the second device comprising respectively a first thermoelectric generator and a second thermoelectric generator, the two thermoelectric generators being in thermal coupling, a first signal is generated within the first device, the first thermoelectric generator is electrically powered as a function of the first signal so as to create a first thermal gradient in the said first generator and a second thermal gradient in the second generator, and a second signal is generated within the second device on the basis of the electrical energy produced by the second thermoelectric generator in response to the said second thermal gradient.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: April 2, 2019
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Pascal Fornara, Christian Rivero
  • Pulse counting circuit
    Patent number: 10243543
    Abstract: A pulse counting circuit receives pulses supplied by a source circuit having at least two inverted pulse signal supply terminals. The circuit includes a first counter to count pulses of a first pulse signal and supply a first count and a second counter to count pulses of a second pulse signal and supply a second count. A selection circuit selects one of the first and second counts.
    Type: Grant
    Filed: November 22, 2016
    Date of Patent: March 26, 2019
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Jean Nicolai, Albert Martinez
  • Integrated circuit comprising an antifuse structure and method of realizing
    Patent number: 10242944
    Abstract: An integrated circuit includes a substrate; an interconnect portion disposed over the substrate, the interconnect portion comprising multiple metallization levels separated by an insulating region; and an antifuse structure coated with a portion of the insulating region, the antifuse structure comprising a beam held at two different points by two arms, a body, and an antifuse insulating zone, the beam, the body and the arms being metal and located within a same metallization level, the body and the beam mutually making contact via the antifuse insulating zone, the antifuse insulating zone configured to undergo breakdown in the presence of a breakdown potential difference between the body and the beam.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: March 26, 2019
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Pascal Fornara, Christian Rivero
  • Method and device for managing information exchange between a main element, for example a NFC controller, and a set of at least two auxiliary elements
    Patent number: 10244372
    Abstract: Device, comprising a main element (ME) and a set of at least two auxiliary elements (SEi), said main element including a master SWP interface (MINT), each auxiliary element including a slave SWP interface (SLINTi) connected to said master SWP interface of said NFC element through a controllably switchable SWP link (LK) and management means (PRM, CTLM, AMGi) configured to control said SWP link switching for selectively activating at once only one slave SWP interface on said SWP link.
    Type: Grant
    Filed: October 27, 2016
    Date of Patent: March 26, 2019
    Assignees: STMICROELECTRONICS (ROUSSET) SAS, STMICROELECTRONICS GMBH
    Inventors: Pierre Rizzo, Alexandre Charles, Juergen Boehler, Thierry Meziache
  • Verification of the resistance of an electronic circuit to side-channel attacks
    Patent number: 10243728
    Abstract: A method of verifying the sensitivity of an electronic circuit executing a Rijndael-type algorithm to side channel attacks, wherein: each block of data to be encrypted or to be decrypted is masked with a first mask before a non-linear block substitution operation is applied based on a substitution box, and is then unmasked with a second mask after the substitution; the substitution box is recalculated, block by block, before the non-linear operation is applied, the processing order of the blocks of the substitution box being submitted to a permutation; and a side channel attack is performed on the steps of recalculating, block by block, the substitution box.
    Type: Grant
    Filed: February 17, 2016
    Date of Patent: March 26, 2019
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventor: Nicolas Bruneau
  • INTEGRATED CIRCUIT CHIP STACK
    Publication number: 20190079133
    Abstract: An integrated circuit chip stack includes a main integrated circuit chip and at least one auxiliary integrated circuit chip. The main integrated circuit chip contains circuit components to be protected. The auxiliary integrated circuit chip is mounted to a surface of the main integrated circuit chip and includes a metal plane connected to ground located opposite the circuit components to be protected. The auxiliary integrated circuit chip further includes at least one insulated conductive track forming a tight pattern opposite the circuit components to be protected. A detection circuit is connected to the at least one conductive track and is configured to detect interruption of the at least one insulated conductive track.
    Type: Application
    Filed: September 7, 2018
    Publication date: March 14, 2019
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Alexandre SARAFIANOS, Thomas ORDAS
  • METHOD FOR DETECTING THINNING OF AN INTEGRATED CIRCUIT SUBSTRATE VIA ITS REAR FACE, AND CORRESPONDING INTEGRATED CIRCUIT
    Publication number: 20190081011
    Abstract: An electronic integrated circuit includes a semiconductor substrate having a rear face. A device for detecting a thinning of the semiconductor substrate via its rear face is formed by a p-n junction that is biased into conduction. Thinning of the substrate is detected by monitoring a current flowing through the p-n junction, and comparing that current to a threshold. In the event the compared current indicates no thinning of the semiconductor substrate, the circuitry for biasing and comparing is deactivated.
    Type: Application
    Filed: September 12, 2018
    Publication date: March 14, 2019
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Alexandre SARAFIANOS, Abderrezak MARZAKI
  • METHOD FOR VERIFYING THE AUTHENTICITY OF A PRODUCT
    Publication number: 20190080336
    Abstract: In order to verify the authenticity of a product associated with a host device, the product contains, in segments of a non-volatile memory, several different functions stored in ciphered fashion. The host device sends a control signal for selecting and activating one of those ciphered functions. The product then deciphers and executes the function. The result of the function execution is then enciphered and communicated back to host device when a decision on product authenticity is made.
    Type: Application
    Filed: November 13, 2018
    Publication date: March 14, 2019
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Denis Farison, Fabrice Romain, Christophe Laurencin
  • Electronic switching device with reduction of leakage currents and corresponding control method
    Patent number: 10230363
    Abstract: A method is used to control an electronic device that includes a switching unit having a main MOS transistor having a substrate, a first conducting electrode and a second conducting electrode coupled to an output terminal. The method includes controlling the main transistor in such a way as to put it into an on state or an off state such that, when the main transistor is in the on state, the substrate and the first conducting electrode of the main transistor are connected to an input terminal and, when the main transistor is in the off state, the first conducting electrode of the main transistor is isolated from the input terminal and a first bias voltage is applied to the first conducting electrode and a second bias voltage is applied to the substrate of the main transistor.
    Type: Grant
    Filed: April 18, 2017
    Date of Patent: March 12, 2019
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Bruno Gailhard, Michel Cuenca
  • Protection of a modular exponentiation calculation
    Patent number: 10229264
    Abstract: A method of protecting a modular exponentiation calculation executed by an electronic circuit using a first register and a second register, successively comprising, for each bit of the exponent: a first step of multiplying the content of one of the registers, selected from among the first register and the second register according to the state of the bit of the exponent, by the content of the other one of the first and second registers, placing the result in said one of the registers; a second step of squaring the content of said other one of the registers by placing the result in this other register, wherein the content of said other one of the registers is stored in a third register before the first step and is restored in said other one of the registers before the second step.
    Type: Grant
    Filed: February 29, 2016
    Date of Patent: March 12, 2019
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventor: Yannick Teglia
  • Stack of layers for protecting against a premature breakdown of interline porous dielectrics within an integrated circuit
    Patent number: 10229880
    Abstract: A stack including a dual-passivation is etched locally so as to reveal contact pads of an integrated circuit which are situated above a last metallization level of an interconnection part of the integrated circuit. This stack serves to protect the integrated circuit against a breakdown of at least one dielectric region, at least in part porous, separating two electrically conducting elements of the interconnection part of the integrated circuit. Such a breakdown may occur due to electrical conduction assisted by the presence of defects within the at least one dielectric region.
    Type: Grant
    Filed: December 14, 2016
    Date of Patent: March 12, 2019
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Christian Rivero, Jean-Philippe Escales
  • Protection of data stored in a volatile memory
    Patent number: 10223532
    Abstract: A method of detecting a cold-boot attack includes transferring, into a first volatile memory of an integrated circuit, a pattern stored in a non-volatile memory of the integrated circuit. Power to the non-volatile memory is periodically interrupted and an indication of a number of errors in the non-volatile memory is generated. The indication of the number of errors is compared to one or more thresholds. An occurrence of a cold-boot attack is detected based on the comparison. The pattern may be reloaded into the first volatile memory before each power interruption. The pattern may be selected so that the number of errors varies according to the integrated circuit temperature.
    Type: Grant
    Filed: June 14, 2017
    Date of Patent: March 5, 2019
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventor: Yannick Teglia
  • INTEGRATED CIRCUIT WITH VERTICALLY STRUCTURED CAPACITIVE ELEMENT, AND ITS FABRICATING PROCESS
    Publication number: 20190067291
    Abstract: A capacitive element includes a trench extending vertically into a well from a first side. The trench is filled with a conductive central section clad with an insulating cladding. The capacitive element further includes a first conductive layer covering a first insulating layer that is located on the first side and a second conductive layer covering a second insulating layer that is located on the first conductive layer. The conductive central section and the first conductive layer are electrically connected to form a first electrode of the capacitive element. The second conductive layer and the well are electrically connected to form a second electrode of the capacitive element. The insulating cladding, the first insulating layer and the second insulating layer form a dielectric region of the capacitive element.
    Type: Application
    Filed: August 24, 2018
    Publication date: February 28, 2019
    Applicants: STMicroelectronics (Rousset) SAS, STMicroelectronics (Crolles 2) SAS
    Inventors: Abderrezak MARZAKI, Arnaud REGNIER, Stephan NIEL, Quentin HUBERT, Thomas CABOUT
  • PROCESS FOR FABRICATING CAPACITIVE ELEMENTS IN TRENCHES
    Publication number: 20190067274
    Abstract: A capacitive element is fabricated by forming a sacrificial trench isolation and directionally etching through the sacrificial trench isolation and into an underlying semiconductor substrate to form an electrode trench. The electrode trench is then clad with an insulating material and filled with a conductive material. The conductive fill provided one capacitor electrode and the semiconductor substrate forms another capacitor electrode, with the insulating material cladding forming the capacitor dielectric layer.
    Type: Application
    Filed: August 24, 2018
    Publication date: February 28, 2019
    Applicant: STMicroelectronics (Rousset) SAS
    Inventor: Abderrezak MARZAKI
  • Distribution of electronic circuit power supply potentials
    Patent number: 10217717
    Abstract: An integrated circuit includes peripheral conductive pads interconnected by a peripheral conductive track within an integrated circuit chip. The integrated circuit chip further includes internal conductive pads interconnected by an internal conductive track within the integrated circuit chip. A conductive bonding wire external to the integrated circuit chip connects the one peripheral conductive pad to one internal conductive pad. A package encapsulates the integrated circuit chip and the conductive bonding wire.
    Type: Grant
    Filed: April 25, 2016
    Date of Patent: February 26, 2019
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Nicolas Froidevaux, Yann Bacher
  • Reading circuit of a long time constant circuit stage and corresponding reading method
    Patent number: 10217503
    Abstract: A reading circuit for a charge-retention circuit stage is provided with a storage capacitor coupled between a first biasing terminal and a floating node, and a discharge element coupled between the floating node and a reference terminal. The reading circuit further has an operational amplifier having a first input terminal that is coupled to the floating node and receives a reading voltage, a second input terminal receives a reference voltage, and an output terminal on which it supplies an output voltage, the value of which is a function of the comparison between the reading voltage and the reference voltage and indicative of a residual charge in the storage capacitor. A shifting stage shifts the value of the reading voltage of the floating node, before the comparison is made between the reading voltage and the reference voltage for supplying the output voltage.
    Type: Grant
    Filed: October 4, 2018
    Date of Patent: February 26, 2019
    Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics (Rousset) SAS, STMicroelectronics S.r.l.
    Inventors: Antonino Conte, Enrico Castaldo, Raul Andres Bianchi, Francesco La Rosa
  • Device for determining the movement of a rotary element, particularly for readings of water and/or gas meters
    Patent number: 10215594
    Abstract: A rotary element is equipped with a pattern representing a reflected binary code on at least three bits. A detection circuit is configured to sense the pattern and deliver an incident signal encoded in reflected binary code on at least three bits. The incident signal is converted by a transcoding circuit into an intermediate signal encoded in reflected binary code on two bits. A decoding stage decodes the intermediate signal and outputs at least one clock signal representing the amount of rotation of the rotary element and a direction signal representing the direction of rotation. A processing circuit determines the movement of the rotary element, and has at least one general purpose timer designed to receive the at least one clock signal and direction signal.
    Type: Grant
    Filed: December 14, 2016
    Date of Patent: February 26, 2019
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Vincent Onde