Patents Assigned to STMicroelectronics (Rousset) SAS
  • DIGITAL-TO-ANALOG CONVERTER
    Publication number: 20180323793
    Abstract: A programmable digital-to-analog converter includes an analog circuit that converts a binary word into a value of analog voltage and a digital circuit that supplies the binary word starting from a maximum value decremented by a decrement value.
    Type: Application
    Filed: April 5, 2018
    Publication date: November 8, 2018
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Vincent ONDE, Jean-Francois LINK
  • METHOD AND DEVICE FOR CONTROLLING THE POWER SUPPLY OF A PROCESSING UNIT
    Publication number: 20180321727
    Abstract: An integrated processing unit is supplied by a power supply voltage present at the terminals of a capacitor configured to supply a maximum permissible voltage drop. A periodic pulse signal is generated having a period that is less than or equal to a current period determined from the maximum permissible voltage drop and a current consumption of the processing unit. The power supply voltage is compared with a threshold voltage at the pulse rate of the periodic pulse signal. A control signal generated from that comparison is delivered to the processing unit and has a first value when the power supply voltage is greater than or equal to the threshold voltage and a second value when the power supply voltage is less than the threshold voltage.
    Type: Application
    Filed: January 30, 2018
    Publication date: November 8, 2018
    Applicant: STMicroelectronics (Rousset) SAS
    Inventor: Bruno Gailhard
  • SWITCH-MODE POWER SUPPLY CONTROL
    Publication number: 20180323695
    Abstract: A control signal is applied to a pulse generating circuit configured to generate pulses that are modulated in width. A circuit provides for slope-compensation of the control signal. The circuit includes a digital-to-analog converter that generates a decreasing sawtooth signal. A triggering circuit operates to trigger steps of the sawtooth signal and resetting the sawtooth signal. The sawtooth signal is reset at a cadence of a frequency of the pulses that are modulated in width.
    Type: Application
    Filed: April 10, 2018
    Publication date: November 8, 2018
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Jean-Francois LINK, Vincent ONDE
  • Transmission and reception methods for a binary signal on a serial link
    Patent number: 10122552
    Abstract: A method can be used for transmission of at least one packet of at least one bit over a serial link capable of taking two different states respectively associated with the two possible logical values of the at least one transmitted bit. Starting from a transmission start time of the at least one bit and up to the expiration of a first portion of a bit time associated with the at least one bit, the link is placed in one of its states depending on the logical value of the at least one bit. Upon the expiration of the first portion of this bit time, a first additional transition is generated over the link so as to place the link in its other state up to the expiration of the bit time.
    Type: Grant
    Filed: September 14, 2015
    Date of Patent: November 6, 2018
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Christophe Arnal, Roland van der Tuijn
  • Method for making a photolithography mask intended for the formation of contacts, mask and integrated circuit corresponding thereto
    Patent number: 10115666
    Abstract: A method for making a photolithography mask for formation of electrically conducting contact pads between tracks of a metallization level and electrically active zones of integrated circuits formed on a semiconductor wafer includes forming a first mask region including first opening zones intended for the formation of the contact pads. The first opening zone has a first degree of opening that is below a threshold. A second mask region including additional opening zones is formed, with the overall degree of opening of the mask being greater than or equal to the threshold.
    Type: Grant
    Filed: March 21, 2014
    Date of Patent: October 30, 2018
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Guilhem Bouton, Patrick Regnier
  • Method and tool for generating a program code configured to perform control flow checking on another program code containing instructions for indirect branching
    Patent number: 10108530
    Abstract: Synchronization points are inserted into a program code to be monitored, and are associated with different branches resulting from execution of an indirect branch instruction. The synchronization points can be accessed by the monitored program code for the purpose of identifying which branch to use during execution of the indirect branch instruction of the monitored program code.
    Type: Grant
    Filed: September 20, 2016
    Date of Patent: October 23, 2018
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Lydie Terras, William Orlando
  • Integrated circuit with detection of thinning via the back face and decoupling capacitors
    Patent number: 10109601
    Abstract: A semiconductor substrate has a back face and a front face and includes a semiconductor well that is electrically isolated from the semiconductor substrate. A device is configured to detect a thinning of the semiconductor substrate from the back face. The device includes at least one trench that extends within the semiconductor well between two peripheral locations from the front face down to a location situated at a distance from a bottom of the semiconductor well. The trench is electrically isolated from the semiconductor well. A detection circuit is configured to measure a physical quantity representative of well electrical resistance between two contact areas respectively situated on either side of the at least one first trench.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: October 23, 2018
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Abderrezak Marzaki
  • Multiplexer structure
    Patent number: 10103721
    Abstract: A logic two-to-one multiplexer includes: two input terminals; one output terminal; a control terminal. Four series-connected two-to-one multiplexers are connected such that a first multiplexer has its inputs connected to the input terminals, a last multiplexer has its output connected to the output terminal, and the other multiplexers have their respective inputs interconnected to the output of the previous multiplexer in the series association. Half of the multiplexers are controlled in reverse with respect to the other half of the multiplexers.
    Type: Grant
    Filed: November 28, 2016
    Date of Patent: October 16, 2018
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Albert Martinez, Michel Agoyan
  • Method for detecting the eventual presence of an object by a contactless reader, and corresponding reader
    Patent number: 10103782
    Abstract: A method can be used for detecting a potential presence of an object by a reader capable of mutually communicating via a contactless communications protocol. An antenna of the reader transmits a magnetic field on a carrier signal having a sub-carrier modulated by a first data sequence. The modulated sub-carrier is non-interpretable by the object. The antenna of the reader receives a signal resulting from the transmission. The reader demodulates the sub-carrier of the resulting signal so as to extract a second data sequence from the resulting signal. The first data sequence and second data sequence are correlated and the potential presence or absence of the object is determined based upon the result of the correlating.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: October 16, 2018
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventor: Alexandre Tramoni
  • Random number generator
    Patent number: 10089079
    Abstract: An integrated random signal generation circuit includes two logic gates, the output of each gate coupled to a respective first input of the other gate via assemblies of delay elements. The respective delays introduced by the assemblies of delay elements are adjustable.
    Type: Grant
    Filed: June 25, 2015
    Date of Patent: October 2, 2018
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Patrick Haddad, Viktor Fischer
  • Electronic device for synchronizing tasks of an electronic appliance
    Patent number: 10089156
    Abstract: An electronic device can be used for synchronizing tasks of an appliance that includes a memory access controller having inputs associated with priority levels. The device includes control circuits configured for receiving signals from events and delivering in response signals for activation of tasks. A configurable interface for external events designed to receive first event signals from at least one circuit of the appliance and to route some of them to the corresponding control circuits as a function of a first law of correspondence. A configurable interface for internal events designed to receive second event signals corresponding to the signals for activation of tasks and to route some of them to the control circuits as a function of a second law of correspondence.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: October 2, 2018
    Assignees: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics (Rousset) SAS
    Inventors: Eric Bernasconi, David Coupe, Ludovic Chotard, Pierre-François Pugibet
  • Method for managing a fail row of the memory plane of a non volatile memory and corresponding memory device
    Patent number: 10083753
    Abstract: A non-volatile memory is erasable by page and equipped with a row redundancy mechanism. In the case of the detection of a defective row of the memory plane, the storing of the address of the row in a non-volatile register is carried out and a redundant row having a new address is assigned. In the case of an attempt to write to the defective row, a write to the redundant row is carried out. When writing to the redundant row, the new content of the redundant row is loaded into a volatile memory and, following an operation for writing to any other row of the memory plane, a re-loading of the new content of the redundant row into the volatile memory.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: September 25, 2018
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Francesco La Rosa, Gineuve Alieri
  • CONFIGURABLE DELAY LINE
    Publication number: 20180269855
    Abstract: A delaying element includes a first XOR logic gate and a second XOR logic gate. A first input of the first XOR logic gate defines an input terminal. A first input of the second XOR logic gate is connected to an output of the first XOR logic gate. An output of the second XOR logic gate defines an output terminal. The second inputs of the first and second XOR logic gates are connected to a second input terminal.
    Type: Application
    Filed: September 11, 2017
    Publication date: September 20, 2018
    Applicant: STMicroelectronics (Rousset) SAS
    Inventor: Albert Martinez
  • Electronic chip
    Patent number: 10079215
    Abstract: An electronic chip including: a plurality of first semiconductor bars of a first conductivity type and of second semiconductor bars of a second conductivity type arranged alternately and contiguously on a region of the first conductivity type; two detection contacts arranged at the ends of each second bar; a circuit for detecting the resistance between the detection contacts of each second bar; insulating trenches extending in the second bars down to a first depth between circuit elements; and insulating walls extending across the entire width of each second bar down to a second depth greater than the first depth.
    Type: Grant
    Filed: October 20, 2017
    Date of Patent: September 18, 2018
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Alexandre Sarafianos, Mathieu Lisart, Jimmy Fort
  • Compact non-volatile memory device
    Patent number: 10074429
    Abstract: A non-volatile memory cell includes a selection transistor having an insulated selection gate embedded in a semiconducting substrate region. A semiconducting source region contacts a lower part of the insulated selection gate. A state transistor includes a floating gate having an insulated part embedded in the substrate region above an upper part of the insulated selection gate, a semiconducting drain region, and a control gate insulated from the floating gate and located partially above the floating gate. The source region, the drain region, the substrate region, and the control gate are individually polarizable.
    Type: Grant
    Filed: February 13, 2018
    Date of Patent: September 11, 2018
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventor: Julien Delalleau
  • Generator of numbers of oscillations
    Patent number: 10075166
    Abstract: A circuit generates a number of oscillations. The circuit includes a first branch with at least one delay line introducing symmetrical delays on rising edges and on falling edges and at least one asymmetrical delay element introducing different delays on rising edges and on falling edges. The circuit further includes a second branch looped back on the first branch and including at least one delay line introducing symmetrical delays on rising edges and on falling edges.
    Type: Grant
    Filed: November 28, 2016
    Date of Patent: September 11, 2018
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Albert Martinez, Michel Agoyan, Jean Nicolai
  • INTEGRATED FUSE DEVICE
    Publication number: 20180254353
    Abstract: A fuse device is formed by a PN junction semiconducting region that is electrically insulated from other portions of an integrated circuit. The fuse device includes a first semiconducting zone having P type of conductivity and a second semiconducting zone having N type of conductivity in contact at a PN junction. First and second electrically conducting contact zones are provided on the first and second semiconducting zone, respectively, without making contact with the PN junction. One of the first and second semiconducting zones is configured with a non-homogeneous concentration of dopants, where a region with a lower value of concentration of dopant is located at the PN junction and a region with a higher value of concentration of dopant is locates at the corresponding electrically conducting contact zone.
    Type: Application
    Filed: September 14, 2017
    Publication date: September 6, 2018
    Applicant: STMicroelectronics (Rousset) SAS
    Inventor: Pascal Fornara
  • System and method for adjusting EEPROM write cycle duration according to supply voltage variation
    Patent number: 10068644
    Abstract: A method of controlling a cycle for writing at least one data item to at least one memory slot of the electrically programmable and erasable read-only memory type disposed in an electronic circuit supplied by a supply voltage includes a controlled increase of the duration of the write cycle in the presence of a decrease in the supply voltage.
    Type: Grant
    Filed: February 25, 2016
    Date of Patent: September 4, 2018
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: François Tailliet, Marc Battista
  • INTEGRATED CIRCUIT WITH DETECTION OF THINNING VIA THE BACK FACE AND DECOUPLING CAPACITORS
    Publication number: 20180247901
    Abstract: A semiconductor substrate has a back face and a front face and includes a semiconductor well that is electrically isolated from the semiconductor substrate. A device is configured to detect a thinning of the semiconductor substrate from the back face. The device includes at least one trench that extends within the semiconductor well between two peripheral locations from the front face down to a location situated at a distance from a bottom of the semiconductor well. The trench is electrically isolated from the semiconductor well. A detection circuit is configured to measure a physical quantity representative of well electrical resistance between two contact areas respectively situated on either side of the at least one first trench.
    Type: Application
    Filed: September 8, 2017
    Publication date: August 30, 2018
    Applicant: STMicroelectronics (Rousset) SAS
    Inventor: Abderrezak Marzaki
  • INTEGRATED CIRCUIT WITH IMPROVED RESISTIVE REGION
    Publication number: 20180247874
    Abstract: An integrated circuit includes a semiconductor substrate with an electrically isolated semiconductor well. An upper trench isolation extends from a front face of the semiconductor well to a depth located a distance from the bottom of the well. Two additional isolating zones are electrically insulated from the semiconductor well and extending inside the semiconductor well in a first direction and vertically from the front face to the bottom of the semiconductor well. At least one hemmed resistive region is bounded by the two additional isolating zones, the upper trench isolation and the bottom of the semiconductor well. Electrical contacts are electrically coupled to the hemmed resistive region.
    Type: Application
    Filed: October 3, 2017
    Publication date: August 30, 2018
    Applicants: STMicroelectronics (Crolles 2) SAS, STMicroelectronics (Rousset) SAS
    Inventors: Benoît Froment, Stephan Niel, Arnaud Regnier, Abderrezak Marzaki