Patents Assigned to STMicroelectronics (Rousset) SAS
  • Publication number: 20140192008
    Abstract: A capacitive touch panel includes first electrodes extending in first direction and second electrodes extending in a second (intersecting) direction. The first electrodes include parallel extending transmit first electrodes and receive first electrodes that are interleaved with each other. The second electrodes include parallel extending transmit second electrodes and receive second electrodes that are interleaved with each other. Transmit circuitry is coupled to the transmit first electrodes and transmit second electrodes. Receive circuitry coupled to the receive first electrodes and receive second electrodes. Processing circuitry controls activation of the transmit and receive circuitry in a manner which supports the making of adjacent line capacitance measurements and intersecting line capacitance measurements. The capacitance measurements are processed to identify and determine location of touches made on or near the capacitive touch panel.
    Type: Application
    Filed: January 8, 2013
    Publication date: July 10, 2014
    Applicants: STMICROELECTRONICS (ROUSSET) SAS, STMICROELECTRONICS K.K.
    Inventors: Maxime Teissier, Cyril Troise
  • Publication number: 20140191385
    Abstract: An integrated circuit includes a number of metallization levels separated by an insulating region disposed over a substrate. A housing includes walls formed from metal portions produced in various metallization levels. A metal device is housed in the housing. An aperture is produced in at least one wall of the housing. An external mechanism outside of the housing is configured so as to form an obstacle to diffusion of a fluid out of the housing through the at least one aperture. At least one through-metallization passes through the external mechanism and penetrates into the housing through the aperture in order to make contact with at least one element of the metal device.
    Type: Application
    Filed: January 7, 2014
    Publication date: July 10, 2014
    Applicant: STMicroelectronics (Rousset) SAS
    Inventor: Antonio Di-Giacomo
  • Publication number: 20140192021
    Abstract: The present disclosure relates to a method for controlling a touch pad, comprising an object locate mode for locating an object on the touch pad comprising steps of: determining a measurement of capacitance of each of the pairs of electrodes of the touch pad, each pair comprising a row electrode and a column electrode transverse to the row electrode, comparing each measurement with a first detection threshold, and if the comparison of at least one measurement with the first threshold reveals the presence of an object on the touch pad, locating the object on the touch pad according to the capacitance measurements, the method comprising a proximity detection mode comprising steps of: determining a measurement representative of the capacitance between one or two electrodes and one or two other electrodes of the touch pad, and comparing a measurement obtained with a second detection threshold different from the first threshold.
    Type: Application
    Filed: March 11, 2014
    Publication date: July 10, 2014
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Laurent Beyly, Cyril Troise, Maxime Teissier
  • Publication number: 20140191329
    Abstract: An integrated circuit includes a MOS transistor having a gate region and source and drain regions separated from the gate region by insulating spacers. At least two metal contact pads respectively contact with two metal silicide regions (for example, a cobalt silicide) which lie within the source and drain regions. The silicide regions are located at the level of lower parts of the two metal contact pads and are separate by a distance from the insulating spacers.
    Type: Application
    Filed: December 30, 2013
    Publication date: July 10, 2014
    Applicant: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Christian Rivero, Roger Delattre
  • Publication number: 20140191578
    Abstract: The current signature of an electronic function is masked by controlling a current source that supplies power for the electronic function is controlled in a dynamically-varying manner. Excess current is detected and compared to a threshold. If the detected excess current meets the threshold, the operation of the electronic function is modified, for example by controlling a clock.
    Type: Application
    Filed: January 6, 2014
    Publication date: July 10, 2014
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Jimmy Fort, Fabrice Marinet
  • Publication number: 20140191179
    Abstract: The disclosure relates to an integrated circuit comprising a transistor comprising first and second conduction terminals and a control terminal. The integrated circuit further comprises a stack of a first dielectric layer, a conductive layer, and a second dielectric layer, the first conduction terminal comprising a first semiconductor region formed in the first dielectric layer, the control terminal comprising a second semiconductor region formed in the conductive layer, and the second conduction terminal comprising a third semiconductor region formed in the second dielectric layer.
    Type: Application
    Filed: January 8, 2014
    Publication date: July 10, 2014
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Philippe Boivin, Francesco La Rosa, Julien Delalleau
  • Publication number: 20140191178
    Abstract: The disclosure relates to a method of fabricating a vertical MOS transistor, comprising the steps of: forming, above a semiconductor surface, a conductive layer in at least one dielectric layer; etching a hole through at least the conductive layer, the hole exposing an inner lateral edge of the conductive layer and a portion of the semiconductor surface; forming a gate oxide on the inner lateral edge of the conductive layer and a bottom oxide on the portion of the semiconductor surface; forming an etch-protection sidewall on the lateral edge of the hole, the sidewall covering the gate oxide and an outer region of the bottom oxide, leaving an inner region of the bottom oxide exposed; etching the exposed inner region of the bottom oxide until the semiconductor surface is reached; and depositing a semiconductor material in the hole.
    Type: Application
    Filed: January 8, 2014
    Publication date: July 10, 2014
    Applicant: STMicroelectronics (Rousset) SAS
    Inventor: Philippe Boivin
  • Patent number: 8772931
    Abstract: An electronic circuit in a package, including two functions, the package orientation activating a single one of the two functions.
    Type: Grant
    Filed: July 17, 2012
    Date of Patent: July 8, 2014
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: François Tailliet
  • Patent number: 8767955
    Abstract: A method for protecting a calculation, by an electronic circuit, of a modular exponentiation of a digital quantity, wherein: a first variable is initialized with a random quantity; at least one second variable is initialized with a value which is a function of the digital quantity; at least for a bit at 1 of an exponent of the modular exponentiation, the first variable is updated by: a) the quotient of its content and a power of the random quantity; and b) the product of its content by that of the second variable; and once all the exponent bits have been processed, the content of the first variable is divided by the random quantity to provide the result of the modular exponentiation.
    Type: Grant
    Filed: July 6, 2012
    Date of Patent: July 1, 2014
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Yannick Teglia
  • Publication number: 20140167908
    Abstract: An integrated circuit comprising a mechanical device for electrical switching comprising a first assembly being thermally deformable and having a beam held at at least two different locations by at least two arms, the beam and the arms being metal and disposed within the same metallization level, and further comprising at least one electrically conducting body. The first assembly has a first configuration at a first temperature and a second configuration at a second temperature different from the first temperature. The beam is out of contact with the electrically conducting body in one configuration in contact with the body in the other configuration. The beam establishes or breaks an electrical link passing through the said at least one electrically conducting body and through the said beam in the different configurations.
    Type: Application
    Filed: February 20, 2014
    Publication date: June 19, 2014
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Pascal Fornara, Christian Rivero, Antonio di-Giacomo
  • Patent number: 8755156
    Abstract: An integrated circuit protected against electrostatic discharges, including input/output pads and first and second power supply rails, and: a thyristor forward-connected between each input/output pad and the second rail, each thyristor including, between its anode gate and its anode, a resistor; between each thyristor and the first rail, a diode having its anode connected to the anode gate of the thyristor and having its cathode connected to the first rail via a resistor for adjusting the triggering; and a triggering device capable of conducting a current between the first and second rails when a positive overvoltage occurs between these rails.
    Type: Grant
    Filed: January 24, 2011
    Date of Patent: June 17, 2014
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: François Tailliet
  • Patent number: 8743670
    Abstract: A data medium of the compact disc type may include medium areas of different types configured to define digital content, and a controllable element having two different states corresponding respectively to the two different types of areas. The controllable element may be configured to take selectively one of its states in response to a command, so as to modify in a controllable manner the content of the data medium.
    Type: Grant
    Filed: October 6, 2011
    Date of Patent: June 3, 2014
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: William Orlando
  • Patent number: 8741742
    Abstract: The disclosure relates to a method of fabricating an integrated circuit of CMOS technology in a semiconductor wafer comprising scribe lines. According to the disclosure, a ground contact pad of the integrated circuit is made in a scribe line of the wafer and is destroyed during a step of individualizing the integrated circuit by singulation of the wafer. A ground contact of the integrated circuit is made on the back side of the integrated circuit when it is assembled in an interconnection package.
    Type: Grant
    Filed: June 8, 2012
    Date of Patent: June 3, 2014
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: François Tailliet
  • Publication number: 20140138814
    Abstract: A method for producing an integrated circuit pointed element is disclosed. An element has a projection with a concave part directing its concavity towards the element. The element includes a first etchable material. A zone is formed around the concave part of the element. The zone includes a second material that is less rapidly etchable than the first material for a particular etchant. The first material and the second material are etched with the particular etchant to form an open crater in the concave part and thus to form a pointed region of the element.
    Type: Application
    Filed: October 9, 2013
    Publication date: May 22, 2014
    Applicant: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Abderrezak Marzaki, Yoann Goasduff, Virginie Bidal, Pascal Fornara
  • Patent number: 8729668
    Abstract: An adjustable resistor formed on a first insulating layer of a substrate, including: a first polysilicon layer covered with a second insulating layer of a first thickness, except in a region where the first polysilicon layer is covered with a thin insulator layer of a second thickness smaller than the first thickness; a second polysilicon layer covering the second insulating layer and the thin insulator layer; on each side of the second insulating layer and at a distance from it, a first and a second conductive vias providing access to the terminals of the resistor on the first polysilicon layer; and a third conductive via providing access to a contacting area on the second polysilicon layer.
    Type: Grant
    Filed: July 19, 2012
    Date of Patent: May 20, 2014
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Pascal Fornara, Arnaud Regnier
  • Patent number: 8729516
    Abstract: A method detects metallic atoms in a fluid. The method includes: placing, in a zone sheltered from light, a photodiode comprising a photosensitive surface in contact with a fluid to analyze; heating the photosensitive surface of the photodiode to a temperature sufficient to allow metallic atoms deposited on the photosensitive surface to migrate through this surface; acquiring a signal relative to the lighting of the photodiode; and determining, from the acquired signal, a measurement representative of a contamination status by metallic atoms of the photodiode.
    Type: Grant
    Filed: October 3, 2011
    Date of Patent: May 20, 2014
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Yannick Marietti
  • Patent number: 8730707
    Abstract: The programming of a read-only memory formed of MOS transistors is set by a mask for forming an insulating layer prior to the forming of contacts of active regions of the transistors. The programming of the read-only memory cannot be determined by visible inspection of the memory.
    Type: Grant
    Filed: March 28, 2008
    Date of Patent: May 20, 2014
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Pascal Fornara
  • Publication number: 20140133517
    Abstract: A device for monitoring the temperature surrounding a circuit, including: a charge storage element; a charge evacuation device; and a thermo-mechanical switch connecting the storage element to the evacuation element, the switch being capable of closing without the circuit being electrically powered, when the temperature exceeds a threshold.
    Type: Application
    Filed: January 22, 2014
    Publication date: May 15, 2014
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Pascal Fornara, Christain Rivero
  • Patent number: 8720600
    Abstract: A method of detecting a fault attack including generating a first signature of a first group of data values by performing a single commutative non-Boolean arithmetic operation between all the data values of the first group; generating a second set of data values by performing a permutation of the first set of data values; generating a second signature of the second group of data values by performing said single commutative non-Boolean arithmetic operation between all the data values of the second group; and comparing the first and second signatures to detect a fault attack.
    Type: Grant
    Filed: November 10, 2010
    Date of Patent: May 13, 2014
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Yannick Teglia
  • Publication number: 20140127873
    Abstract: A method for fabricating at least one cell of a semiconducting component includes positioning a first conducting polysilicon-type layer on a substrate, above an insulating oxide-type layer. The production of at least one trench within the first conducting layer is included to form two electrically unlinked distinct conducting parts intended to form two transistor gates of respectively two distinct twin cells.
    Type: Application
    Filed: November 7, 2013
    Publication date: May 8, 2014
    Applicant: STMICROELECTRONICS (ROUSSET) SAS
    Inventor: Philippe BOIVIN