Patents Assigned to STMicroelectronics (Rousset) SAS
  • Publication number: 20140347931
    Abstract: An EEPROM circuit includes a data reception register and a column decoder. A buffer memory having a size corresponding to the size of a data page is included between the data reception register and the column decoder.
    Type: Application
    Filed: May 21, 2014
    Publication date: November 27, 2014
    Applicant: STMicroelectronics (Rousset) SAS
    Inventor: François Tailliet
  • Patent number: 8896368
    Abstract: An electromagnetic transponder includes an antenna circuit, a load, and a charge pump transistor having a current path coupled between the antenna circuit and the load. During operation, a retromodulated signal is transmitted at a first level by biasing the charge pump transistor during a first time period such that an impedance of the antenna circuit has a first impedance value and current flows from the antenna circuit to the load. A retromodulated signal at a second level is transmitted by biasing the charge pump transistor during a second time period such that the impedance of the antenna circuit has a second impedance value different than the first impedance value and current flows from the antenna circuit to the load. The retromodulated signals are transmitted at the first and second levels in a sequence determined to transmit information from the electromagnetic transponder.
    Type: Grant
    Filed: November 26, 2013
    Date of Patent: November 25, 2014
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Gilles Bas, Christophe Moreaux, Gary Seigneuret
  • Patent number: 8891310
    Abstract: The disclosure relates to an electrically erasable and programmable memory comprising at least one word of memory cells with first and second control gate transistors in parallel to apply a control gate voltage to the memory cells of the word. The memory also comprises s first control circuit to supply a first control voltage to a control terminal of the first control gate transistor through a first current limiter, and a second control circuit to supply a second control voltage to a control terminal of the second control gate transistor through second current limiter.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: November 18, 2014
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Francois Tailliet
  • Patent number: 8892798
    Abstract: A method of communication between a master circuit and two slave circuits over a serial bus wherein: the two slave circuits simultaneously transmit their associated identifiers; the two slave circuits simultaneously transmit the inverse of these identifiers; and each slave circuit exploits the combinations present on the bus to determine an order of communication between the two circuits.
    Type: Grant
    Filed: October 5, 2011
    Date of Patent: November 18, 2014
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: François Tailliet, Yvon Bahout
  • Patent number: 8887269
    Abstract: Authentication system comprising an input device comprising a plurality of input elements configured for inputting respectively characters in response to an input of a sequence of at least one character carried out by a user, the input device comprising at least one determination means coupled to at least one input element in order to determine a force exerted on the said at least one input element, the system comprising a recording means for recording a series of at least one force exerted on the said at least one input element, a memory configured for storing a series of at least one reference force, and comparison means configured for comparing the series of at least one exerted force with the series of at least one reference force.
    Type: Grant
    Filed: April 21, 2011
    Date of Patent: November 11, 2014
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Yannick Teglia
  • Patent number: 8884689
    Abstract: A low pass filter comprises a filter input node configured to receive a first logic signal, a filter output node configured to supply a second logic signal, a resistive element comprising a first terminal coupled to the input node and a second terminal coupled to the output node, and a capacitive element comprising a first terminal coupled to the output node and a second terminal. The filter further comprises an inverting gate having a first terminal coupled to the input node and a second terminal coupled to the second terminal of the capacitive element.
    Type: Grant
    Filed: April 23, 2013
    Date of Patent: November 11, 2014
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Francois Tailliet, Marc Battista
  • Patent number: 8884289
    Abstract: An integrated circuit comprising a mechanical device for electrical switching comprising a first assembly being thermally deformable and having a beam held at at least two different locations by at least two arms, the beam and the arms being metal and disposed within the same metallization level, and further comprising at least one electrically conducting body. The first assembly has a first configuration at a first temperature and a second configuration at a second temperature different from the first temperature. The beam is out of contact with the electrically conducting body in one configuration in contact with the body in the other configuration. The beam establishes or breaks an electrical link passing through the said at least one electrically conducting body and through the said beam in the different configurations.
    Type: Grant
    Filed: February 20, 2014
    Date of Patent: November 11, 2014
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Pascal Fornara, Christian Rivero, Antonio di-Giacomo
  • Patent number: 8881090
    Abstract: The technological fabrication of the integrated circuit includes a fabrication of the integrated circuit in a reduced technological version of a native technology including at least a first dimensional compensation applied to the reduced channel length and to the reduced channel width of each transistor originating from a transistor, referred to as a “minimum transistor”, designed in the native technology and having in this native technology an initial channel length equal to a minimum length for the native technology and an initial channel width equal to a minimum width for the native technology. The fabrication obtains a transistor having a channel length equal, to a given precision, to the initial channel length and a channel width equal, to a given precision, to the initial channel width.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: November 4, 2014
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Guilhem Bouton, Virginie Bidal
  • Publication number: 20140319653
    Abstract: An integrated circuit includes a substrate. A fixed main capacitor electrode is disposed in a metal layer overlying the substrate. A second main capacitor electrode is disposed in a metal layer and spaced from the fixed main capacitor electrode. A movable capacitor electrode is disposed adjacent the fixed main capacitor electrode. The movable capacitor electrode is switchable between a first configuration in which the movable capacitor electrode and fixed main capacitor electrode are mutually spaced out in such a manner as to form an auxiliary capacitor electrically connected to the main capacitor. In a second configuration, the movable capacitor electrode and the fixed main capacitor electrode are in electrical contact in such a manner as to give a second capacitive value.
    Type: Application
    Filed: April 29, 2014
    Publication date: October 30, 2014
    Applicant: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Pascal Fornara, Christian Rivero
  • Patent number: 8873745
    Abstract: A method for protecting a calculation on an elliptic curve, by an electronic circuit, wherein a point of an elliptic curve is multiplied by a digital quantity, comprising the steps of: initializing a first variable with a value which is a function of a random quantity; initializing at least a second variable with a value which is a function of the digital quantity; at least for a bit at 1 of the digital quantity, the first variable is updated by: a) subtracting a multiple of the random quantity; and b) adding the content of the second variable; and once all the bits of the digital quantity have been processed, subtracting from the first variable the product of the point by the random quantity to provide the result.
    Type: Grant
    Filed: July 6, 2012
    Date of Patent: October 28, 2014
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Yannick Teglia
  • Patent number: 8872177
    Abstract: A charge flow circuit for a time measurement, including a plurality of elementary capacitive elements electrically in series, each elementary capacitive element leaking through its dielectric space.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: October 28, 2014
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Francesco La Rosa, Pascal Fornara
  • Patent number: 8874816
    Abstract: A method of transmission over a serial bus, between a master circuit and two slave circuits, wherein each slave circuit makes the transmission of a first one of two binary states depend on the absence of a transmission of the second binary state by the other slave circuit.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: October 28, 2014
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: François Tailliet
  • Patent number: 8867217
    Abstract: A circuit including a flexible substrate and at least one electric element attached to the substrate, the substrate including at least one cavity arranged near the electric element and helping to break or distort the electric element in response to a flexion or stretching of the substrate. Application in particular is to the manufacture of tear-proof electronic micromodules.
    Type: Grant
    Filed: January 29, 2010
    Date of Patent: October 21, 2014
    Assignee: STMicroelectronics Rousset SAS
    Inventors: Francis Steffen, Gilbert Assaud
  • Patent number: 8854135
    Abstract: An operational amplifier may include a differential stage comprising two transistors whose gates are respectively linked to the two inputs of the operational amplifier. The sources of the two transistors may be linked to a first current source whose delivered current depends negatively on temperature variations and to a second current source whose delivered current is proportional to absolute temperature. The sum of these two currents may be less dependent on temperature, in that this link of the sources of the two transistors with the two current sources is effected respectively by way of two resistors, and in that the current which passes through the two transistors is imposed of proportional with temperature type, so as to allow substantially temperature-independent elimination of the offset voltage of the operational amplifier while obtaining a temperature-independent constant gain-bandwidth product.
    Type: Grant
    Filed: January 29, 2013
    Date of Patent: October 7, 2014
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Michel Cuenca, Laurent Truphemus
  • Patent number: 8853615
    Abstract: A method for measuring radiation of energy photons, such as ultraviolet radiation, on a surface, may include programming at least one transistor by at least transmitting an electric charge to it. The method may further include measuring an electrical quantity of the at least one transistor receiving radiation of energy photons and estimating, based on this electrical quantity, an amount of radiation received.
    Type: Grant
    Filed: July 19, 2012
    Date of Patent: October 7, 2014
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Julia Castellan, Philippe Boivin
  • Publication number: 20140291858
    Abstract: A method for making a photolithography mask for formation of electrically conducting contact pads between tracks of a metallization level and electrically active zones of integrated circuits formed on a semiconductor wafer includes forming a first mask region including first opening zones intended for the formation of the contact pads. The first opening zone has a first degree of opening that is below a threshold. A second mask region including additional opening zones is formed, with the overall degree of opening of the mask being greater than or equal to the threshold.
    Type: Application
    Filed: March 21, 2014
    Publication date: October 2, 2014
    Applicant: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Guilhem BOUTON, Patrick Regnier
  • Patent number: 8848917
    Abstract: A method for verifying the integrity of a key implemented in a symmetrical ciphering or deciphering algorithm, including the steps of complementing to one at least the key; and verifying the coherence between two executions of the algorithm, respectively with the key and with the key complemented to one.
    Type: Grant
    Filed: May 14, 2009
    Date of Patent: September 30, 2014
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Pierre-Yvan Liardet, Yannick Teglia
  • Patent number: 8843065
    Abstract: The device may include a contactless element and a set of least two auxiliary elements. Each auxiliary element may include a slave SWP interface connected to a same master SWP interface of the contactless element through a SWP link, and a management module configured for activating at once only one slave SWP interface on the SWP link.
    Type: Grant
    Filed: October 26, 2011
    Date of Patent: September 23, 2014
    Assignees: STMicroelectronics (Rousset) SAS, STMicroelectronics Design and Application GmbH
    Inventors: Laurent Degauque, Jürgen Böhler, Alexandre Charles, Pierre Rizzo
  • Publication number: 20140273836
    Abstract: An anticollision method for an NFC device wherein, in reader mode, a variation of a piece of information representative of the amplitude of the signal in an antenna of the device is monitored, and if this piece of information exceeds a threshold, the device is switched to the card mode.
    Type: Application
    Filed: March 13, 2014
    Publication date: September 18, 2014
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Pierre Rizzo, Nathalie Vallespin, Emmanuel Papart
  • Patent number: 8835923
    Abstract: The semiconductor wafer for a silicon-on-insulator integrated circuit comprises an insulating region located between a first semiconductor substrate intended to receive the integrated circuit and a second semiconductor substrate containing at least one buried layer comprising at least one metal silicide.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: September 16, 2014
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Pascal Fornara