Abstract: The present disclosure relates to a method of controlling the manufacturing of integrated circuits, comprising steps of determining parameters that are characteristic of a curve of radiation intensity applied to a semiconductor wafer through a mask, in critical zones of structures to be formed on the wafer, for each of the critical zones, placing a measuring point in a multidimensional space each dimension of which corresponds to one of the characteristic parameters, placing control points in the multidimensional space that are spread around an area delimited by the measuring points, so as to delimit an envelope surrounding the area, for each control point, defining control structures each corresponding to a control point, generating a mask containing the control structures, applying a process involving the generated mask to a semiconductor wafer, and analyzing the control structures transferred to the wafer to detect any defects therein.

Abstract: A method manufactures semiconductor chips each comprising a component implanted in the semiconductor. The method includes collectively implanting components onto a front face of a semiconductor wafer and fixing a plate of a transparent material onto the front face of the wafer. Fixing the plate of transparent material is preceded by a step of depositing, on the front face of the wafer, at least one layer of polymer material forming an optical filter. Application is particularly to the manufacturing of imagers.

Abstract: A method of read or write access by an electronic component of data, including generating a first secret key for a first data of an ordered list of data to access, and for each data of the list, following the first data, generating a distinct secret key by means of a deterministic function applied to a secret key generated for a previous data of the list, and the application of a cryptographic operation to each data to be read or to be written of the list, carried out by using the secret key generated for the data.

Abstract: A circuit for detecting a fault injection in an integrated circuit including: at least one logic block for performing a logic function of said integrated circuit; an isolation block coupled to receive a signal to be processed and an isolation enable signal indicating a functional phase and a detection phase of the logic block, the isolation block applying, during the functional phase, the signal to be processed to at least one input of the logic block, and during the detection phase, a constant value to the input of the logic block; and a detection block adapted to monitor, during the detection phase, the state of the output signal of the logic block, and to generate an alert signal in case of any change in the state of the output signal.

Abstract: A sense amplifier is disclosed comprising a first sense input, a second sense input, a latch, a first p-channel control transistor arranged to electrically power a first section of the latch and having a gate terminal linked to the first sense input, and a second p-channel control transistor arranged to electrically power a second section of the latch and having a gate terminal linked to the second sense input. Application may be in particular to low power embedded memories.

Abstract: The disclosure relates to an integrated circuit comprising a data buffer circuit comprising first and second transistors coupled to a contact pad and third and fourth transistors. A first bias voltage is applied on a conduction terminal of the third transistor and a second bias voltage is applied on a conduction terminal of the fourth transistor. A third bias voltage less than the second bias voltage is applied on a control terminal of the first transistor and a fourth bias voltage greater than the first bias voltage is applied on a control terminal of the second transistor. Application notably for the production of a so-called “High Speed” USB port.

Abstract: A method of authentication of a terminal generating a magnetic field, by a transponder including an oscillating circuit from which a D.C. voltage is generated, wherein the transponder: receives first data relative to the current in an oscillating circuit of the terminal, measured by the terminal for a first value of the resistive load of the transponder; and exploits these first data and second data relative to the level of said D.C. voltage, respectively measured for the first resistive load value and for a second resistive load value.

Abstract: A method of authentication of a terminal generating a magnetic field by a transponder including an oscillating circuit from which a D.C. voltage is generated, wherein at least one quantity depending on the coupling between the transponder and the terminal is compared with at least one reference value.

Abstract: The present disclosure relates to an electrically erasable and programmable memory comprising rows of memory cells to store words of N bits each, bit lines and word lines, wherein a row of memory cells comprises a first group of memory cells to store collectively erasable words, and at least one second group of memory cells to store one individually erasable word.

Abstract: A method of authentication, by a terminal generating a magnetic field, of a transponder located in this field, wherein: first data, relative to the current in an oscillating circuit of the terminal, measured by the terminal for a first value of the resistive load of the transponder, are transmitted to the transponder; second corresponding data are evaluated by the transponder for a second value of the resistive load and are transmitted to the terminal; and said second data are compared with third corresponding data, measured by the terminal for the second value of the resistive load.

Abstract: A method for evaluating the current coupling factor between an electromagnetic transponder and a terminal, wherein a ratio between data representative of a voltage across an oscillating circuit of the transponder and obtained for two pairs of inductive and capacitive values of this oscillating circuit is compared with one or several thresholds, the two pairs of values preserving a tuning of the oscillating circuit to a same frequency.

Abstract: A element for identifying an integrated circuit chip having identical diffused resistors connected as a Wheatstone bridge.

Abstract: A method for evaluating the current coupling factor between an electromagnetic transponder and a terminal, wherein a ratio between data, representative of a voltage across an oscillating circuit of the transponder and obtained for two values of the resistive load, is compared with one or several thresholds.

Abstract: A device for detecting the thinning down of the substrate of an integrated circuit chip, including, in the active area of the substrate, bar-shaped diffused resistors connected as a Wheatstone bridge, wherein: first opposite resistors of the bridge are oriented along a first direction; the second opposite resistors of the bridge are oriented along a second direction; and the first and second directions are such that a thinning down of the substrate causes a variation of the imbalance value of the bridge.

Abstract: A memory device may include a memory plane including a group of memory cells configured to store a block of bits including data bits and parity bits, and a detector for detecting a fault injection including a reader to read each bit, and a first checker to perform, when reading a block, a parity check based on the read value of each data and parity bit. The memory plane may include reference memory cells arranged between some of the memory cells to create packets of m memory cells. Each reference memory cell may store a reference bit and each packet of m memory cells may store m bits of the associated block, when m is greater than 1, with different parities. The detector may further include a second checker to perform, when reading the block, a check on the value of each reference bit.

Abstract: A method manufactures semiconductor chips each comprising a component implanted in the semiconductor. The method includes collectively implanting components onto a front face of a semiconductor wafer and fixing the a plate of a transparent material onto the front face of the wafer. Fixing the plate of transparent material is preceded by a step of depositing, on the front face of the wafer, at least one layer of polymer material forming an optical filter. Application is particularly to the manufacturing of imagers.

Abstract: An integrated circuit may include a region containing a thermoelectric material and be configured to be subjected to a temperature gradient resulting from a flow of an electric current in a part of the integrated circuit during its operation, and an electrically conducting output coupled to the region for delivering the electrical energy produced by thermoelectric material.

Abstract: A method of generating electrical energy in an integrated circuit that may include setting into motion a (3D) three-dimensional enclosed space in the integrated circuit. The 3D enclosed space may include a piezoelectric element and a free moving object therein. The method may also include producing the electrical energy from impact between the free moving object and the piezoelectric element during the motion.

Abstract: An integrated circuit including a substrate of a semiconductor material having first and second opposite surfaces and including active areas leveling the first surface. The integrated circuit includes a device of protection against laser attacks, the protection device includes at least one first doped region extending between at least part of the active areas and the second surface, a device for biasing the first region, and a device for detecting an increase in the current provided by the biasing device.

Abstract: A method for protecting a generation, by an electronic circuit, of at least one prime number by testing the prime character of successive candidate numbers, including: for each candidate number: the calculation of a reference number involving at least one first random number, and at least one primality test based on modular exponentiation calculations; and for a candidate number having successfully passed the primality test: a test of consistency between the candidate number and its reference number.